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From:   "Tian, Kevin" <kevin.tian@intel.com>
To:     Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>
CC:     "x86@kernel.org" <x86@kernel.org>, Joerg Roedel <joro@8bytes.org>,
        "Will Deacon" <will@kernel.org>,
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        "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
        Marc Zyngier <maz@kernel.org>,
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        Allen Hubbe <allenbh@gmail.com>,
        "Ahmed S. Darwish" <darwi@linutronix.de>
Subject: RE: [patch V2 12/33] PCI/MSI: Add support for per device MSI[X]
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Thread-Topic: [patch V2 12/33] PCI/MSI: Add support for per device MSI[X]
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Thread-Index: AQHY/bbibHqIjpCS0EGXLo0J/f6SVK5MFjUwgABPTYCAAKovgIAANyYA
Date:   Thu, 24 Nov 2022 01:08:33 +0000
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> From: Thomas Gleixner <tglx@linutronix.de>
> Sent: Thursday, November 24, 2022 5:50 AM
>=20
> >> This is general PCI MSI logic. So an open related to my rely to patch0=
2,
> >> is it correct for PCI core to assume that the real parent imposes all =
the
> >> restrictions and there is no need to further go down the hierarchy?
> >
> > That was my working assumption and it turned out to be correct with bot=
h
> > x86 and ARM.
>=20
> As a follow up, I went through some of the other architectures,
> especially the places which have extra limitations and it turns out that
> the restriction comes always from the direct parent.
>=20
> If that ever changes then we need a callback which lets us evaluate the
> resulting capabilities through the hierarchy. That's nothing which can
> be evaluated directly.
>=20
> Just look at the x86 hierarchy with IR. IR allows multi PCI-MSI, but the
> vector domain does not. Who is right? That's a decision which is made in
> the particular hierarchy.

make sense.

>=20
> For now it's valid that the direct MSI parent has the proper set
> available.
>=20

probably above can be marked out in the comment.