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Date:   Thu, 24 Nov 2022 10:27:45 +0530
From:   Viresh Kumar <viresh.kumar@linaro.org>
To:     "xiaowu.ding" <xiaowu.ding@jaguarmicro.com>
Cc:     Tushar.Khandelwal@arm.com, jassisinghbrar@gmail.com,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] driver:mhuv2:Fix data mode rx startup problem
Message-ID: <20221124045745.yycyoxw2drk4rw6k@vireshk-i7>
References: <20221124032701.2163-1-xiaowu.ding@jaguarmicro.com>
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On 24-11-22, 11:27, xiaowu.ding wrote:
> From: Xiaowu Ding <xiaowu.ding@jaguarmicro.com>
> 
> When using the arm mhuv2 data transfer mode , sometimes the sender can
> not send data anymore ,and sender will blocking because of receiver did not
> clear the stat_clear.
> 
> The test scene:
> A is sender(poll mode) ; B is receiver (interrupt mode)
> When A send msg to B ,but B did not have register the mailbox . The B will
> miss the message ,and will not clear the stat_clear. So the sender A will
>  be send blocking status and can not send again anymore.
> 
> So the patch just clear the stat_clear within the rx startup function. Just
> Drop the last message before receiver will not be ready for receiver .
> 
> Signed-off-by: Xiaowu Ding <xiaowu.ding@jaguarmicro.com>
> ---
>  drivers/mailbox/arm_mhuv2.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c
> index a47aef8df52f..7aef458f0b18 100644
> --- a/drivers/mailbox/arm_mhuv2.c
> +++ b/drivers/mailbox/arm_mhuv2.c
> @@ -327,6 +327,14 @@ static int mhuv2_data_transfer_rx_startup(struct mhuv2 *mhu,
>  {
>  	struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
>  	int i = priv->ch_wn_idx + priv->windows - 1;
> +	const int windows = priv->windows;
> +	int j, idx;
> +
> +	/* clear the rx stat_clear */
> +	for (j = 0; j < windows; j++) {
> +		idx = priv->ch_wn_idx + j;
> +		writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[idx].stat_clear);
> +	}

Since this is already done in mhuv2_data_transfer_read_data(), I am not sure why
it is required again.

>  
>  	/*
>  	 * The protocol mandates that all but the last status register must be

-- 
viresh