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Date:   Thu, 24 Nov 2022 09:07:06 +0100
From:   Michael Walle <michael@walle.cc>
To:     Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Cc:     greg.malysa@timesys.com,
        Tudor Ambarus <tudor.ambarus@microchip.com>,
        Pratyush Yadav <pratyush@kernel.org>,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] These are the required patches I found while adding
In-Reply-To: <20221123211335.126417-1-nathan.morrison@timesys.com>
References: <20221123211335.126417-1-nathan.morrison@timesys.com>
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Hi Nathan,

Am 2022-11-23 22:13, schrieb Nathan Barrett-Morrison:
> 1) The core framework needs some additional logic for 8S-8S-8S to pass 
> through
> succesfully.
> 
> 2) The IS25LX256 chip needs added to the SPI part table along with
> various fixups

Unfortunately, I can't make any sense of this series. First of all, the
IS25LX256 [1] doesn't support 8S-8S-8S, only 8D-8D-8D and 1S-8S-8S, see
ch. 4. Confused, I've looked at your octal str enable function and it 
writes
0xc7 to the volatile configuration register 0x00. According to the 
datasheet,
that is the enable for the octal DTR mode.

Please explain your problem and your motivation in the cover 
letter/commit
message and how you fix it.

[1] https://www.issi.com/WW/pdf/25LX-WX256-128.pdf

-michael