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From:   Thomas Gleixner <tglx@linutronix.de>
To:     "Tian, Kevin" <kevin.tian@intel.com>,
        LKML <linux-kernel@vger.kernel.org>
Cc:     "x86@kernel.org" <x86@kernel.org>, Joerg Roedel <joro@8bytes.org>,
        Will Deacon <will@kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Marc Zyngier <maz@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jason Gunthorpe <jgg@mellanox.com>,
        "Jiang, Dave" <dave.jiang@intel.com>,
        Alex Williamson <alex.williamson@redhat.com>,
        "Williams, Dan J" <dan.j.williams@intel.com>,
        Logan Gunthorpe <logang@deltatee.com>,
        "Raj, Ashok" <ashok.raj@intel.com>, Jon Mason <jdmason@kudzu.us>,
        Allen Hubbe <allenbh@gmail.com>
Subject: RE: [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store)
 support
In-Reply-To: <BN9PR11MB5276549A90576254ACCCBED48C0F9@BN9PR11MB5276.namprd11.prod.outlook.com>
References: <20221121083657.157152924@linutronix.de>
 <20221121091328.026206487@linutronix.de>
 <BN9PR11MB5276549A90576254ACCCBED48C0F9@BN9PR11MB5276.namprd11.prod.outlook.com>
Date:   Thu, 24 Nov 2022 10:10:41 +0100
Message-ID: <87leo0d8fi.ffs@tglx>
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On Thu, Nov 24 2022 at 03:10, Kevin Tian wrote:

>> From: Thomas Gleixner <tglx@linutronix.de>
>> Sent: Monday, November 21, 2022 10:38 PM
>> 
>> The IMS domains have a few constraints:
>> 
>>   - The index space is managed by the core code.
>> 
>>     Device memory based IMS provides a storage array with a fixed size
>>     which obviously requires an index. But there is no association between
>>     index and functionality so the core can randomly allocate an index in
>>     the array.
>> 
>>     Queue memory based IMS does not have the concept of an index as the
>>     storage is somewhere in memory. In that case the index is purely
>>     software based to keep track of the allocations.
>
> 'Queue' could be a HW queue or SW queue. Is it clearer to just use
> 'system memory based IMS" here?

Yes