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Date:   Thu, 24 Nov 2022 11:40:20 +0000
From:   Mark Brown <broonie@kernel.org>
To:     Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Cc:     greg.malysa@timesys.com,
        "open list:SPI SUBSYSTEM" <linux-spi@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] spi: cadence-quadspi: Add upper limit safety check to
 baudrate divisor
Message-ID: <Y39YJL02jFbkEMqw@sirena.org.uk>
References: <20221123211705.126900-1-nathan.morrison@timesys.com>
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On Wed, Nov 23, 2022 at 04:17:05PM -0500, Nathan Barrett-Morrison wrote:

> +	/* Maximum baud divisor */
> +	if (div > CQSPI_REG_CONFIG_BAUD_MASK)
> +		div = CQSPI_REG_CONFIG_BAUD_MASK;

This will fix the overflow of the divisor but it means that we'll be
generating a faster clock than the device asked for which might lead to
problems.  We should at the very least warn, though returning an error
would be safer.  Ideally we'd be able to adjust the input clock to the
SPI controller to allow us to divide out an appropriate clock but that's
more disruptive.

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