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Message-ID: <896278fb-1af8-609b-cd64-f3f59530e9b0@quicinc.com>
Date:   Thu, 24 Nov 2022 21:24:18 +0530
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Subject: Re: [PATCH v2 02/10] arm64: dts: qcom: Add base SM8550 dtsi
To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Abel Vesa <abel.vesa@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Neil Armstrong <neil.armstrong@linaro.org>
CC:     Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>
References: <20221124135646.1952727-1-abel.vesa@linaro.org>
 <20221124135646.1952727-3-abel.vesa@linaro.org>
 <351fa466-90cb-b73f-a2a4-749bc3529e22@quicinc.com>
 <0a119446-4ec1-46ce-68e5-f177f9cb49e3@linaro.org>
From:   Sai Prakash Ranjan <quic_saipraka@quicinc.com>
In-Reply-To: <0a119446-4ec1-46ce-68e5-f177f9cb49e3@linaro.org>
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On 11/24/2022 9:10 PM, Konrad Dybcio wrote:
> 
> 
> On 24.11.2022 16:39, Sai Prakash Ranjan wrote:
>> Hi,
>>
>> On 11/24/2022 7:26 PM, Abel Vesa wrote:
>>> Add base dtsi for SM8550 SoC and includes base description of
>>> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
>>> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
>>> interconnect, thermal sensor, cpu cooling maps and SMMU nodes
>>> which helps boot to shell with console on boards with this SoC.
>>>
>>> Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>> ---
>>
>> <snip>...
>>
>>> +    timer {
>>> +        compatible = "arm,armv8-timer";
>>> +        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>>
>> This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2.
> Does non-CrOS 8550 FW allow Linux to boot in EL2?
> 

Sadly no, which is why this entry always gets wrong downstream.

Thanks,
Sai