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Date:   Thu, 24 Nov 2022 18:34:11 +0100
From:   Samuel Ortiz <sameo@rivosinc.com>
To:     Conor Dooley <conor@kernel.org>
Cc:     "Hongren (Zenithal) Zheng" <i@zenithal.me>,
        Palmer Dabbelt <palmer@rivosinc.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Atish Patra <atishp@rivosinc.com>,
        Anup Patel <anup@brainfault.org>,
        Eric Biederman <ebiederm@xmission.com>,
        Kees Cook <keescook@chromium.org>, linux-mm@kvack.org,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-api@vger.kernel.org,
        Michael Kerrisk <mtk.manpages@gmail.com>,
        linux-man@vger.kernel.org, Jiatai He <jiatai2021@iscas.ac.cn>,
        Heiko Stuebner <heiko@sntech.de>
Subject: Re: [PATCH v3 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto
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On Thu, Nov 24, 2022 at 05:20:37PM +0000, Conor Dooley wrote:
> On 24/11/2022 17:12, Samuel Ortiz wrote:
> > [You don't often get email from sameo@rivosinc.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> > 
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On Thu, Nov 24, 2022 at 11:55:01AM +0000, Conor Dooley wrote:
> >> On Thu, Nov 24, 2022 at 11:47:30AM +0100, Samuel Ortiz wrote:
> >>
> >>> Patch #1 is definitely needed regardless of which interface we pick for
> >>> exposing the ISA strings to userspace.
> >>
> >> I took another look at #1, and I feel more confused about what
> >> constitutes canonical order than I did before! If you know better than
> >> I, and you probably do since you're interested in these 6 month old
> >> patches, some insight would be appreciated!
> > 
> > Assuming we don't go with hwcap, I dont think the order of the
> > riscv_isa_ext_id enum matters that much?
> 
> The chief put it in canonical order so that's good enough for me!
> 
> > 
> > iiuc we're building the cpuinfo string from the riscv_isa_ext_data
> > array, and I think the current code is incorrect:
> > 
> > static struct riscv_isa_ext_data isa_ext_arr[] = {
> >     __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> >     __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> >     __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> >     __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> >     __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> >     __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> >     __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
> > };
> > 
> > zicbom and zihintpause should come before supervisor level extensions.
> > I'm going to send a patch for that.
> 
> idk, Palmer explicitly re-ordered this:
> https://lore.kernel.org/linux-riscv/20220920204518.10988-1-palmer@rivosinc.com/
> 
> By my reading of the isa manual, what Palmer did is correct as
> those are not "Additional Standard Extensions". /shrug

Hmm, by their name (Z[a-b]+) they are Additional Standard Extensions.
What am I missing?

Cheers,
Samuel.
>