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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n16-20020a170902e55000b00186af7a393asi5986969plf.327.2022.11.25.16.55.31; Fri, 25 Nov 2022 16:55:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=s2TYdjTs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230016AbiKZAYF (ORCPT + 85 others); Fri, 25 Nov 2022 19:24:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229570AbiKZAYD (ORCPT ); Fri, 25 Nov 2022 19:24:03 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1840850D68; Fri, 25 Nov 2022 16:24:03 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A146061184; Sat, 26 Nov 2022 00:24:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0CABC4347C; Sat, 26 Nov 2022 00:24:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669422242; bh=5toZeTHuclM1Oqu4FwGv8OsMLJIOueWsu96ihEcja7Q=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=s2TYdjTszuownAOhegyo/pU6TQOAJCrRDzZYjdYBb+Y4QmuaPc0NJk4r9pIiKNw3k 6C8wv/Je/Sh+ZYVIa0Mnfn5c4f7OtgOFNCPwhP+yeaFsg28xB84lp6wXkGU/pvn/Vj M3CNu6DssogyBrW1f9L6uO+ILtKQSXr1gQt/0qvSrlKfSpXIOsqeSiEOV3K3IDRRIf +vVrb5acH6IF8hmStcADAe3Wb/fEPfSDJnjaek4Wn0AKE5+HExVxYb1odz6lwCFGpI +X9rRpJld6AJ41I0KoGYPn+9QRetV7QT/MzzpSaLglOCMX67PVdTH9AhZvs/d5YGPx YG970q1j7aLRQ== Received: by mail-ej1-f49.google.com with SMTP id ho10so13454018ejc.1; Fri, 25 Nov 2022 16:24:01 -0800 (PST) X-Gm-Message-State: ANoB5pk6WzE9KQu5qtPbA5GPlQ+PyQqC5HvwcKZB2Zbfmam5TUWsFpRf gx8jwIiBklk3m0P1DnnXDK5mnSipNKXeiEaFXi8= X-Received: by 2002:a17:907:9856:b0:780:8144:a41f with SMTP id jj22-20020a170907985600b007808144a41fmr35405801ejc.189.1669422240081; Fri, 25 Nov 2022 16:24:00 -0800 (PST) MIME-Version: 1.0 References: <20221125234656.47306-1-samuel@sholland.org> <20221125234656.47306-12-samuel@sholland.org> In-Reply-To: <20221125234656.47306-12-samuel@sholland.org> From: Guo Ren Date: Sat, 26 Nov 2022 08:23:48 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 11/12] riscv: Add the Allwinner SoC family Kconfig option To: Samuel Holland Cc: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Rob Herring , Heiko Stuebner , Jisheng Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara , Albert Ou , Anup Patel , Atish Patra , Christian Hewitt , Conor Dooley , Heinrich Schuchardt , Linus Walleij , Paul Walmsley , Stanislav Jakubek Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reviewed-by: Guo Ren On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland wrote: > > Allwinner manufactures the sunxi family of application processors. This > includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8 > SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs. > > The first SoC in the sun20i series is D1, containing a single T-HEAD > C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM. > > Most peripherals are shared across the entire chip family. In fact, the > ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible > with the D1s. > > This means many existing device drivers can be reused. To facilitate > this reuse, name the symbol ARCH_SUNXI, since that is what the existing > drivers have as their dependency. > > Reviewed-by: Heiko Stuebner > Tested-by: Heiko Stuebner > Signed-off-by: Samuel Holland > --- > > Changes in v2: > - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing > > arch/riscv/Kconfig.socs | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..4c1dc2ca11f9 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -26,6 +26,15 @@ config SOC_STARFIVE > help > This enables support for StarFive SoC platform hardware. > > +config ARCH_SUNXI > + bool "Allwinner sun20i SoCs" > + select ERRATA_THEAD if MMU && !XIP_KERNEL > + select SIFIVE_PLIC > + select SUN4I_TIMER > + help > + This enables support for Allwinner sun20i platform hardware, > + including boards based on the D1 and D1s SoCs. > + > config SOC_VIRT > bool "QEMU Virt Machine" > select CLINT_TIMER if RISCV_M_MODE > -- > 2.37.4 > -- Best Regards Guo Ren