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[2620:137:e000::1:20]) by mx.google.com with ESMTP id oz20-20020a1709077d9400b0078de44dd61fsi6234298ejc.990.2022.11.26.08.25.17; Sat, 26 Nov 2022 08:25:37 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=OAsemZit; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229630AbiKZQEQ (ORCPT + 84 others); Sat, 26 Nov 2022 11:04:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbiKZQD6 (ORCPT ); Sat, 26 Nov 2022 11:03:58 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EAB2B98; Sat, 26 Nov 2022 08:03:57 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CE2486069D; Sat, 26 Nov 2022 16:03:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9319C433C1; Sat, 26 Nov 2022 16:03:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669478636; bh=I3oNLAP3k0VDPBsE+OwGRfWZ2bU2j6dd+5v0b5Q9tmA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=OAsemZityeg5XfYsehUAUZJDHWgGIQwOc0fwhwONNlKW5SpvMrbLZ4Hez8HrbTZza t+0DV4D7yxIc8gFG2TzkAxI5VikhOcK2+OsSuBJ4HGpQQwCAmsD4DAEllVpgDK7iEN ob9kpDW82FfvJ6DVTuYs+Sv85igEyzmxo9w5I/JRQ848B7VuUEgHqZBhHafXAvs+gB LPUVd4xgoWfsDq2gbXnyxCRgQlzjaux5QOU/4zFboieGEuUfWmfgcuAfnvyH0pOTIa Ci6VQmTGjeYk6maCYRo5jIWoVa995b+B4LPktjN+PULOsv0o7id/DCjWPo4omIgl/+ BrWdCDDsDMFcg== Date: Sat, 26 Nov 2022 16:03:49 +0000 From: Conor Dooley To: Samuel Holland Cc: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Rob Herring , Heiko Stuebner , Jisheng Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara , Albert Ou , Anup Patel , Atish Patra , Christian Hewitt , Conor Dooley , Guo Ren , Heinrich Schuchardt , Linus Walleij , Paul Walmsley , Stanislav Jakubek Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Message-ID: References: <20221125234656.47306-1-samuel@sholland.org> <20221125234656.47306-5-samuel@sholland.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221125234656.47306-5-samuel@sholland.org> X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 25, 2022 at 05:46:48PM -0600, Samuel Holland wrote: > D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based > on a single die, or at a pair of dies derived from the same design. > > D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and > T113 contain a pair of Cortex-A7's. Is this "additionally contain" or a case of the D1 is the R528 but with s/arm/riscv/? It's the latter, right? > D1 and R528 are the full version of > the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP > variants. > > Because the original design supported both ARM and RISC-V CPUs, some > peripherals are duplicated. In addition, all variants except D1s contain > a HiFi 4 DSP with its own set of peripherals. > > The devicetrees are organized to minimize duplication: > - Common perhiperals are described in sunxi-d1s-t113.dtsi > - DSP-related peripherals are described in sunxi-d1-t113.dtsi > - RISC-V specific hardware is described in sun20i-d1s.dtsi > - Functionality unique to the D1 variant is described in sun20i-d1.dtsi > > The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells > values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC. Modulo the warnings I replied to the cover with & one minor comment below: Reviewed-by: Conor Dooley > Signed-off-by: Samuel Holland > --- > > Changes in v2: > - Split into separate files for sharing with D1s/R528/T113 > - Use SOC_PERIPHERAL_IRQ macro for interrupts > - Rename osc24M to dcxo and move the frequency to the board DTs > - Drop analog LDOs due to the missing binding > - Correct tcon_top DSI clock reference > - Add DMIC, DSI controller, and DPHY (bindings are in linux-next) > - Add CPU OPP table > > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++ > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++ > .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 + > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 844 ++++++++++++++++++ > 4 files changed, 1001 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > new file mode 100644 > index 000000000000..c8815cbf0b46 > --- /dev/null > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -0,0 +1,844 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +// Copyright (C) 2021-2022 Samuel Holland > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + dcxo: dcxo-clk { > + compatible = "fixed-clock"; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; Since this is a "must", can you drop the clock-frequency = <0> here so that if someone doesn't override it in their board dt-validate complains? Thanks, Conor. > + clock-output-names = "dcxo"; > + #clock-cells = <0>; > + }; > +