Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp14097401rwb; Sun, 27 Nov 2022 17:33:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf4ZFhAY/ReWCxcLmMm23ebcoLtoFgloMywKMgCMaBTAhq5fAf1FjKDoR7lspLpC+pW/QduV X-Received: by 2002:a17:907:989a:b0:7c0:7bd1:6436 with SMTP id ja26-20020a170907989a00b007c07bd16436mr53890ejc.718.1669599212169; Sun, 27 Nov 2022 17:33:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669599212; cv=none; d=google.com; s=arc-20160816; b=fvqIenmulhhbZm4ahqNpGIEg9/UO9LNOdg+LxH87RaifWbtHaaOi2JgO47TEJnkq1C elgGp7wxQqaqVkWzitdYUksTrOsWNosO3czFFexFpx6yW9QBuBzq+OJH1364j6GBF5do MVa6lrygqTwsXpPc5UeK+rGksz8BQRTkkaP/4EZ6LoR+Hkopd2sZrA1KevgE7s88bViu yNcAcwf1faoDUddSftN9gRNaXjYtFcXXc5IoN8dPAHsazMAX7jCuQZNg43VXlIVU15ox uX11/l/rob+XBlb+4pGdy8r2T8EdyGyJyetR4gklgBKkbIlGj7AtoMG3KCLMARr3z6rz plOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id; bh=OMMVwWyyC1DXtRWKfM3vHY+oVRGKkDhvZpKsXKy6WSY=; b=zPXTG1GDPpYgmWJ9k+s4WGOGc8dHYYj5QnyXXvG87YvH3fZ11ZgRxdlYJiprYyd4Bz X5gBMUCl3SX76rOkbpbLlNpbF3LcQEE1VDLfUuLBKVPY54vTPEDOF8JmiqvlLnK9SVQ9 y50HAN2CwLjcT82fg7J5IpLEW5Cae7ZptuZVTqXhvFc7dY2WcrrCO9fGyuex1QwNjvys N/0XaipqB5VmKe4LLiT7tI0WIBpZDBNe+Q+D/qM8UbKAxQkMhHex08DG/sbH30JlPSYr gtOindQ/QBGPLCeWevUrgqAl4FKp1FI4z70Q22fxZEM8G6MyjK9z9umzkCUjrnspTYRv etsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t21-20020a50d715000000b0046a09ce4d1csi7919069edi.349.2022.11.27.17.33.11; Sun, 27 Nov 2022 17:33:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229676AbiK1BPP (ORCPT + 85 others); Sun, 27 Nov 2022 20:15:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229694AbiK1BPL (ORCPT ); Sun, 27 Nov 2022 20:15:11 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6C7F764B; Sun, 27 Nov 2022 17:15:07 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 1793424E194; Mon, 28 Nov 2022 09:15:06 +0800 (CST) Received: from EXMBX065.cuchost.com (172.16.6.65) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 28 Nov 2022 09:15:05 +0800 Received: from [192.168.125.66] (183.27.97.81) by EXMBX065.cuchost.com (172.16.6.65) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 28 Nov 2022 09:15:04 +0800 Message-ID: <05ade4a9-6ae2-6e3a-5223-270b24e6ea24@starfivetech.com> Date: Mon, 28 Nov 2022 09:15:51 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v2 3/5] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl Content-Language: en-US To: Krzysztof Kozlowski , Hal Feng , , , CC: Conor Dooley , Palmer Dabbelt , "Rob Herring" , Krzysztof Kozlowski , Linus Walleij , Emil Renner Berthing , References: <20221118011108.70715-1-hal.feng@starfivetech.com> <20221118011108.70715-4-hal.feng@starfivetech.com> <7f78e57a-d9be-b1e9-d161-40b1f66e3804@linaro.org> From: Jianlong Huang In-Reply-To: <7f78e57a-d9be-b1e9-d161-40b1f66e3804@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [183.27.97.81] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX065.cuchost.com (172.16.6.65) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 21 Nov 2022 09:44:00 +0100, Krzysztof Kozlowski wrote: > On 18/11/2022 02:11, Hal Feng wrote: >> From: Jianlong Huang >> >> Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller. >> >> Signed-off-by: Jianlong Huang >> Signed-off-by: Hal Feng >> --- >> .../pinctrl/starfive,jh7110-aon-pinctrl.yaml | 134 ++++++++++++++++++ >> 1 file changed, 134 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml >> new file mode 100644 >> index 000000000000..1dd000e1f614 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml >> @@ -0,0 +1,134 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 Aon Pin Controller >> + >> +description: | >> + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. >> + >> + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO4 >> + can be multiplexed and have configurable bias, drive strength, >> + schmitt trigger etc. >> + Some peripherals have their I/O go through the 4 "GPIOs". This also >> + includes PWM. >> + >> +maintainers: >> + - Jianlong Huang >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-aon-pinctrl >> + >> + reg: >> + maxItems: 1 >> + >> + reg-names: >> + items: >> + - const: control >> + >> + clocks: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + gpio-controller: true >> + >> + "#gpio-cells": >> + const: 2 >> + >> + interrupts: >> + maxItems: 1 >> + description: The GPIO parent interrupt. > > Same comments apply plus one more. Will fix, drop this description. > >> + >> + interrupt-controller: true >> + >> + "#interrupt-cells": >> + const: 2 >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - gpio-controller >> + - "#gpio-cells" >> + - interrupts >> + - interrupt-controller >> + - "#interrupt-cells" > > "required:" goes after patternProperties. Will fix. > >> + >> +patternProperties: >> + '-[0-9]+$': > > Same comment. Will fix. Keep consistent quotes, use ' > >> + type: object >> + patternProperties: >> + '-pins$': >> + type: object >> + description: | >> + A pinctrl node should contain at least one subnode representing the >> + pinctrl groups available on the machine. Each subnode will list the >> + pins it needs, and how they should be configured, with regard to >> + muxer configuration, system signal configuration, pin groups for >> + vin/vout module, pin voltage, mux functions for output, mux functions >> + for output enable, mux functions for input. >> + >> + properties: >> + pinmux: >> + description: | >> + The list of GPIOs and their mux settings that properties in the >> + node apply to. This should be set using the GPIOMUX macro. >> + $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux" >> + >> + bias-disable: true >> + >> + bias-pull-up: >> + type: boolean >> + >> + bias-pull-down: >> + type: boolean >> + >> + drive-strength: >> + enum: [ 2, 4, 8, 12 ] >> + >> + input-enable: true >> + >> + input-disable: true >> + >> + input-schmitt-enable: true >> + >> + input-schmitt-disable: true >> + >> + slew-rate: >> + maximum: 1 >> + >> + additionalProperties: false >> + >> + additionalProperties: false >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; > > Same comment. Will fix. Use 4 spaces for example indentation. > >> + >> + gpioa: gpio@17020000 { >> + compatible = "starfive,jh7110-aon-pinctrl"; >> + reg = <0x0 0x17020000 0x0 0x10000>; >> + reg-names = "control"; >> + resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>; >> + interrupts = <85>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + #gpio-cells = <2>; >> + gpio-controller; >> + }; >> + }; >> + >> +... > Best regards, Jianlong Huang