Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Chester Lin <clin@suse.com>
To:     "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Jan Petrous <jan.petrous@nxp.com>, Andrew Lunn <andrew@lunn.ch>
Cc:     Chester Lin <clin@suse.com>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Giuseppe Cavallaro <peppe.cavallaro@st.com>,
        Jose Abreu <joabreu@synopsys.com>, netdev@vger.kernel.org,
        s32@nxp.com, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>,
        Matthias Brugger <mbrugger@suse.com>
Subject: [PATCH v2 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver
Date:   Mon, 28 Nov 2022 13:49:17 +0800
Message-Id: <20221128054920.2113-3-clin@suse.com>
In-Reply-To: <20221128054920.2113-1-clin@suse.com>
References: <20221128054920.2113-1-clin@suse.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?VLRxUtXycK94x6kM77Uwc3bkUS3kyXPSqtIQDGFzYUEeQJLUUEbIGNBWYKIP?=
 =?us-ascii?Q?VHxJKiSeY28lzGoIlAx4ISRMJF08Jf+SVO3N67kSwOH3vmN/eTOdc5+wRYl4?=
 =?us-ascii?Q?iaiHLdIcmaMZzjnF105SLhu0LvrQqOzUP4Ma7qXxPUgOA5m3LkzqvSmji6XL?=
 =?us-ascii?Q?PIcC3TzZoCPp+XuWQya3r/lxDHX5r4kr58avhiLprCKRLEbkz6fGM4IJ0yp4?=
 =?us-ascii?Q?x9hsie6X6M/YV6WJij7UdmANty408ClIwG2b3dJB37HQmAIPuiKhJdYP1EbU?=
 =?us-ascii?Q?kE/5c8cl9YC8NcG9YARAO0igP4y77N3QL4/7MQZ+b0YuYG6ebkvx5/Ot9oJl?=
 =?us-ascii?Q?jUn3Pd1HyQVuiQmRqrVk9KO1ztelGxSGi/CyspA7iX1XJkkBADfonoPFl++6?=
 =?us-ascii?Q?uuxffuHz84TlHEc3XBArc/rwY/gLPkwgQnsk9fadeh/5g6jxiq9u0tpxSn+1?=
 =?us-ascii?Q?C6fRh+rBrzvomsJ8SSxs4iJvS+dyA6rryDWbN2/GorhkMxJxf5IlMCeGFWJP?=
 =?us-ascii?Q?qSnyZk3GnjK/ZrXMBKTMmoyy3Qeam9IxflA/YG1XT05jxk2Fowi+7UE4VRM/?=
 =?us-ascii?Q?DW+6PHA0S83ggMG9P0yySAUXxQtf+bzzRw7u0ITm1XQj7GPZqOKBCHy+mCkb?=
 =?us-ascii?Q?h9BgUGLbREVQlY3q2Z3gKoNfjr5Egt9dnW9ttQMFUNDY6tQWrsn9QwD+A1u9?=
 =?us-ascii?Q?kcuaDlDok9w7MirbymT1kJ35dxg+9vitcOkL5MnkC+q8uXE9/GGEu/QWoeEF?=
 =?us-ascii?Q?4k9O8zHI/luKsAwuWaiC42HMA410aVCA3utbVSU+x/lzilCiVmJfNQ989bma?=
 =?us-ascii?Q?m0ck8Vy5kWQiWGSV+CWnRhg1pg8lc4oa7V7wnlPzM5Vp36El38VfnZAAxaA/?=
 =?us-ascii?Q?A7fHbTaY/lx+jO19gzxTMWTn9J2HaVhdxyQmor8+ugAffI5swGCtUONhbJcO?=
 =?us-ascii?Q?amgZyekZboY1+ioDQkr0SGsz7GgNZRGGVDLSbN/KwtykyhlYtuw54Ga/Pilf?=
 =?us-ascii?Q?WE1vp1cRLEQg2RLkY8m7Sw/BikfulW7sP1MyL8LHMdkuS7mTwPu8PVzJ/TOl?=
 =?us-ascii?Q?lncw3u/PyVrcJcVjiBP68IXeP74Jo/SWTpSgFRXMhDe1+uN/VuqiCI7RhyAZ?=
 =?us-ascii?Q?S4MFHn7PTc605LM7Mqs9hdmtcZQzkUlMx8SRgC/2NoCj4Osk2eD9DGVZP7eV?=
 =?us-ascii?Q?yAbUi3RqDYC7vgK+KDWApw7Q2DD72HM3I+mnQETgpa8x+o1z2jkhvu5NAmKh?=
 =?us-ascii?Q?36jbzoUBiToLYDNwEs6ALg8zQ49PB7j/kcSZR7BF8MDWiLeNNwKv0YZAfOVo?=
 =?us-ascii?Q?61VtUpzp2WAsVfDTf9sJyTl+acJ30z46iAK6bCU82b25RJtanFZdlrqW2reS?=
 =?us-ascii?Q?4R0/A4zsLBva69cCKM85yAq16qsJDzFg6VLT7AUs1laf5JiGtJQiBjzuCOl8?=
 =?us-ascii?Q?5c7Pb2VaqVxsWzr5eazqS7MBZrGoU0iSxsSrQHKs/MjEiTrIDjuv8BKsiAus?=
 =?us-ascii?Q?SEXGFuCibtLAk17g0/JP2gYko1PyNleShYLCFSFMJGtn9N07wwDpfhtKtejQ?=
 =?us-ascii?Q?nHdyPuPwoEeSAG6UawORmHtZo2dxw+LMWOXrsBom37UQ9Rdbv8i3ARmhP6p2?=
 =?us-ascii?Q?qU1L7FJM9Mdz7UTWP/Bos8EHPzJOcWOn6dK2C14TVM7H?=
X-OriginatorOrg: suse.com
X-MS-Exchange-CrossTenant-Network-Message-Id: f3a04ac4-c047-4de7-c834-08dad1045da8
X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2022 05:49:51.1200
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: zG4gk7q+fFeLbMx7WiBRsW1X0CM4AMkc7C1Eesen0NYWk5EhnpiSNwSzujmVFKPO
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7655
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham
        autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common
Chassis.

Signed-off-by: Jan Petrous <jan.petrous@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
---

Changes in v2:
  - Fix schema issues.
  - Add minItems to clocks & clock-names.
  - Replace all sgmii/SGMII terms with pcs/PCS.

 .../bindings/net/nxp,s32cc-dwmac.yaml         | 135 ++++++++++++++++++
 1 file changed, 135 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml

diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml
new file mode 100644
index 000000000000..c6839fd3df40
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021-2022 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NXP S32CC DWMAC Ethernet controller
+
+maintainers:
+  - Jan Petrous <jan.petrous@nxp.com>
+  - Chester Lin <clin@suse.com>
+
+allOf:
+  - $ref: "snps,dwmac.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - nxp,s32cc-dwmac
+
+  reg:
+    items:
+      - description: Main GMAC registers
+      - description: S32 MAC control registers
+
+  dma-coherent: true
+
+  clocks:
+    minItems: 5
+    items:
+      - description: Main GMAC clock
+      - description: Peripheral registers clock
+      - description: Transmit PCS clock
+      - description: Transmit RGMII clock
+      - description: Transmit RMII clock
+      - description: Transmit MII clock
+      - description: Receive PCS clock
+      - description: Receive RGMII clock
+      - description: Receive RMII clock
+      - description: Receive MII clock
+      - description:
+          PTP reference clock. This clock is used for programming the
+          Timestamp Addend Register. If not passed then the system
+          clock will be used.
+
+  clock-names:
+    minItems: 5
+    items:
+      - const: stmmaceth
+      - const: pclk
+      - const: tx_pcs
+      - const: tx_rgmii
+      - const: tx_rmii
+      - const: tx_mii
+      - const: rx_pcs
+      - const: rx_rgmii
+      - const: rx_rmii
+      - const: rx_mii
+      - const: ptp_ref
+
+  tx-fifo-depth:
+    const: 20480
+
+  rx-fifo-depth:
+    const: 20480
+
+required:
+  - compatible
+  - reg
+  - tx-fifo-depth
+  - rx-fifo-depth
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    #define S32GEN1_SCMI_CLK_GMAC0_AXI
+    #define S32GEN1_SCMI_CLK_GMAC0_TX_PCS
+    #define S32GEN1_SCMI_CLK_GMAC0_TX_RGMII
+    #define S32GEN1_SCMI_CLK_GMAC0_TX_RMII
+    #define S32GEN1_SCMI_CLK_GMAC0_TX_MII
+    #define S32GEN1_SCMI_CLK_GMAC0_RX_PCS
+    #define S32GEN1_SCMI_CLK_GMAC0_RX_RGMII
+    #define S32GEN1_SCMI_CLK_GMAC0_RX_RMII
+    #define S32GEN1_SCMI_CLK_GMAC0_RX_MII
+    #define S32GEN1_SCMI_CLK_GMAC0_TS
+
+    soc {
+      #address-cells = <1>;
+      #size-cells = <1>;
+
+      gmac0: ethernet@4033c000 {
+        compatible = "nxp,s32cc-dwmac";
+        reg = <0x4033c000 0x2000>, /* gmac IP */
+              <0x4007C004 0x4>;    /* S32 CTRL_STS reg */
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "macirq";
+        phy-mode = "rgmii-id";
+        tx-fifo-depth = <20480>;
+        rx-fifo-depth = <20480>;
+        dma-coherent;
+        clocks = <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_TX_PCS>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RGMII>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RMII>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_TX_MII>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_RX_PCS>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RGMII>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RMII>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_RX_MII>,
+                 <&clks S32GEN1_SCMI_CLK_GMAC0_TS>;
+        clock-names = "stmmaceth", "pclk",
+                      "tx_pcs", "tx_rgmii", "tx_rmii", "tx_mii",
+                      "rx_pcs", "rx_rgmii", "rx_rmii", "rx_mii",
+                      "ptp_ref";
+
+        gmac0_mdio: mdio {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          compatible = "snps,dwmac-mdio";
+
+          ethernet-phy@4 {
+            reg = <0x04>;
+          };
+        };
+      };
+    };
-- 
2.37.3