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Date:   Mon, 28 Nov 2022 22:34:38 +0800
From:   Jisheng Zhang <jszhang@kernel.org>
To:     Conor Dooley <conor@kernel.org>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>,
        Ilpo =?utf-8?B?SsOkcnZpbmVu?= <ilpo.jarvinen@linux.intel.com>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org
Subject: Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC
Message-ID: <Y4TG/iM0ibf65Iua@xhacker>
References: <20221127132448.4034-1-jszhang@kernel.org>
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 <Y4TF8FzX19puws37@xhacker>
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On Mon, Nov 28, 2022 at 10:30:15PM +0800, Jisheng Zhang wrote:
> On Sun, Nov 27, 2022 at 05:36:53PM +0000, Conor Dooley wrote:
> > On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote:
> > > Hey Jisheng,
> > > 
> > > On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> > > > Add Jisheng Zhang as Bouffalolab SoC maintainer.
> > > > 
> > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > ---
> > > >  MAINTAINERS | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > > 
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 00ff4a2949b8..a6b04249853c 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -17729,6 +17729,15 @@ F:	arch/riscv/
> > > >  N:	riscv
> > > >  K:	riscv
> > > >  
> > > > +RISC-V BOUFFALOLAB SOC SUPPORT
> > > > +M:	Jisheng Zhang <jszhang@kernel.org>
> > > > +L:	linux-riscv@lists.infradead.org
> > > > +S:	Maintained
> > > > +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > > > +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> > > > +F:	arch/riscv/boot/dts/bouffalolab/
> > > > +F:	drivers/tty/serial/bflb_uart.c
> > > 
> > > I think I asked last time but I didn't see an answer on lore or my
> > > mailbox - if you intend sending Arnd PRs for this stuff, please add a
> 
> Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd
> if there are two or more commits/patches; If there's only one patch, I
> asked Arnd for picking it up directly. So in bouffalolab SoC case, I
> want to do similar, but with one difference -- if there's only one
> patch, may I ask you for picking it up directly?

That's to say: If there are two or more commits/patches, I will send
Arnd PRs; If there's only one commit/patch, I will ask your help to
picking it up directly.

> 
> > > git tree here. Otherwise, LMK and I'll bundle it with the other "misc
> 
> Hmm, is "git tree" necessary?
> 
> > > riscv devicetree" stuff.
> > 
> > I forgot:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> > > >  RISC-V MICROCHIP FPGA SUPPORT
> > > >  M:	Conor Dooley <conor.dooley@microchip.com>
> > > >  M:	Daire McNamara <daire.mcnamara@microchip.com>
> > > > -- 
> > > > 2.38.1
> > > > 
> > > > 
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > linux-riscv@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv