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Date:   Mon, 28 Nov 2022 23:20:11 +0100
From:   Borislav Petkov <bp@alien8.de>
To:     Uros Bizjak <ubizjak@gmail.com>
Cc:     x86@kernel.org, linux-kernel@vger.kernel.org,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH] x86/boot: Remove x86_32 PIC using ebx workaround
Message-ID: <Y4U0GwlLgAuxu3WF@zn.tnic>
References: <20221104124546.196077-1-ubizjak@gmail.com>
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On Fri, Nov 04, 2022 at 01:45:46PM +0100, Uros Bizjak wrote:
> Current minimum required version of GCC is version 5.1 which allows
> reuse of PIC hard register on x86/x86-64 targets [1]. Remove
> obsolete workaround that was needed for earlier GCC versions.
> 
> [1] https://gcc.gnu.org/gcc-5/changes.html

Thanks for the doc pointer.

Lemme see if I understand this commit message correctly:

SysV i386 ABI says that %ebx is used as the base reg in PIC. gcc 5 and
newer can handle all possible cases properly where inline asm could
clobber the PIC reg. I.e., it is able to deal with the "=b" constraint
where an insn can overwrite %ebx and it'll push and pop around that
statement.

So far so good.

Why then does this matter for x86-64 where PIC addressing is done
rip-relative so %rbx is normal reg there?

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette