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Wed, 30 Nov 2022 02:21:28 -0500 (EST) Message-ID: Date: Wed, 30 Nov 2022 01:21:27 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux ppc64le; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Content-Language: en-US To: Jisheng Zhang Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Greg Kroah-Hartman , Jiri Slaby , =?UTF-8?Q?Ilpo_J=c3=a4rvinen?= References: <20221127132448.4034-1-jszhang@kernel.org> <20221127132448.4034-7-jszhang@kernel.org> From: Samuel Holland Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree In-Reply-To: <20221127132448.4034-7-jszhang@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/27/22 07:24, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..f4b170ccc32e > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang > + */ > + > +#include > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { It's unfortunate that the SDK/documentation calls this peripheral both UART0 and UART3. I don't know if we can/should put the "M0" and "D0" bus peripherals in the same DT; it seems like most of the "M0" peripherals are not accessible from the C906. But if we did, this would conflict with the other UART0. > + compatible = "bouffalolab,bl808-uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; There's a clock controller with a mux and a gate between the crystal and the UART. I'm not sure what the policy is about adding "fake" suppliers before the real supplier has a binding defined. Unfortunately, Bouffalolab threw everything and the kitchen sink into the GLB register space, so that complicates defining the binding for the clock/reset controller part. > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, The C906 PLIC has an M-mode context, so 0xffffffff is not correct. This should reference the M-mode external interrupt. > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so this value should be at least that. Regards, Samuel > + }; > + }; > +};