Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Vadym Kochan <vadym.kochan@plvision.eu>
To:     Hu Ziji <huziji@marvell.com>, Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Elad Nachman <enachman@marvell.com>,
        Chris Packham <chris.packham@alliedtelesis.co.nz>,
        Vadym Kochan <vadym.kochan@plvision.eu>
Subject: [PATCH v2 3/3] mmc: xenon: Fix 2G limitation on AC5 SoC
Date:   Wed, 30 Nov 2022 15:37:47 +0200
Message-Id: <20221130133747.3777340-4-vadym.kochan@plvision.eu>
In-Reply-To: <20221130133747.3777340-1-vadym.kochan@plvision.eu>
References: <20221130133747.3777340-1-vadym.kochan@plvision.eu>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?1Ri3SdvDbobbIrccMxz3BqqRJwg9QmjM8VOC2UvncxXHx0wJAyvgnAspivg+?=
 =?us-ascii?Q?jIWw2xxzBbNb3hko1p7WxXbEOo6eZYzRrAFQi5yUphBLmzZoxs6W7lyiQMVN?=
 =?us-ascii?Q?JqQMXNrfM6Xs+IejC4CQlMFZOlMgNyyI+AXqU88OiPGyYBvznkYPFKlaRFj1?=
 =?us-ascii?Q?1uXw/bUSs2Uuke6xxXGH9FG9ATUjUopQlritdlZiD84JqnR+dHG4dyQMClKI?=
 =?us-ascii?Q?sIFAjMUQrsXvQ1E1UNj8M/T1ytLtBTx/Bu8rPozPqsYCLfW9x6VaazE7shqA?=
 =?us-ascii?Q?miCcdMrMNkguFV+at2+2KgGxGaitlw78t/sNb8jlQfAbrKzajHED8Q4fdglo?=
 =?us-ascii?Q?287jRcvKQ4ufiaQ5kVSMJz7rg8dL/RPAATlckhIp/zBjMbyNfxzawCn4b42F?=
 =?us-ascii?Q?2nrCpzTWRFcEgGNWUbCvv7l3YIaMQjd4SDHYs1KRo66XhDV5FpBpPOm5iwI3?=
 =?us-ascii?Q?yiXsIEhVT13p3+maQgxgHaMEDIjOyK2aWlLbT5oqU249MAWYy7cPfLxqMsAd?=
 =?us-ascii?Q?jwQKO9M2i5y2AHH34MCgDartOXy/Y824MAQF2n8k2ubSzq/drwdqyYSnkCSw?=
 =?us-ascii?Q?HdN17YG8p1RC7uexv7HDG6ketuA/ku+6FV5/b7L7sULwoOe8RntANxRWu/0h?=
 =?us-ascii?Q?+ZkOAqBsSZnXhD96FzlunjVithXrE/toD6Z/9BP3Lsn3g/EpSa+JQSl4SPsO?=
 =?us-ascii?Q?xhKJbdCn622dKYsvuz+nXEnsVz1jCFtdGNYPNeZirQx2avEpYCWuWw9OvIe2?=
 =?us-ascii?Q?RiyI5Asjy5xXUqZGZ5UhkY8R1amLFUB3F1aSsiA6sGKBpBL0gMHPxZL8qFQh?=
 =?us-ascii?Q?UUvMI/O+l8YhtSqnmR6AyRebe0K9ruTCRs95syI0gy/wn47OK+nheDU2u572?=
 =?us-ascii?Q?SMrPHEHv/netrpYC8j4dxvOnT/oij3Kl88gHbf16LaiSsuPFX8DnDnxIzddH?=
 =?us-ascii?Q?OX9ZP2P+4m3mj2ShROV1/PxmxpdhLx/OPKBVTMTGJhScdkeBK/oIqpkd9Gp2?=
 =?us-ascii?Q?Q/tKhsNz610wB7z8VBjEGunWy+NqDA7eB9u6n1AsxV+dcmdEMs93UY/AjpdS?=
 =?us-ascii?Q?mcTj7WibxXO++kkSnd6JegqlKuBLEdYtkkRGE04XSPV2gFKvHcPQvBVlWhWs?=
 =?us-ascii?Q?ns31plxxjYuAxVDMnTIrVE21utbfgJiFRSvwLm2+k+1YUM0ceSE3MfOJPsh2?=
 =?us-ascii?Q?An9YftBKwrgeEQCtIQ9hXAcERmcH9HgT9GOlx6P/03nh0aWZrJxzzYu44oMW?=
 =?us-ascii?Q?fgUjqOjOTZaXof+4arj68H7cyJxjLALzXC9CUdUGVfkj682SNcQZ3Drz4S1L?=
 =?us-ascii?Q?7p1MNs76hjNHIDgecPTNXB01qtqWeNsTvC+f4iFXVmasb16cNYI6HcUsyDS8?=
 =?us-ascii?Q?2mgjkevCIeW855H5yCrDblGU7EX0BIIY1CZru7RjbvlrRTmQ2f9euswGExjZ?=
 =?us-ascii?Q?Tes5X0EG9QRGTUzsHtMpAsseuVk0A3zTRvJ/DJY5eE1zmoph0MGtQ7C3wCoR?=
 =?us-ascii?Q?BFKIwlaRAGnB/HYdjrwCZZnoAytlh6G7jtgiDBz8XbweMlDcoAjvuVWfvozb?=
 =?us-ascii?Q?IqI65EIYjR08sriCBiXM0Mn2bBg5px4tRypZP6rY+sLQkSh2f2gZLdG9YEMq?=
 =?us-ascii?Q?RQ=3D=3D?=
X-OriginatorOrg: plvision.eu
X-MS-Exchange-CrossTenant-Network-Message-Id: 3b48161c-9a10-4a32-88fe-08dad2d81da6
X-MS-Exchange-CrossTenant-AuthSource: VI1P190MB0317.EURP190.PROD.OUTLOOK.COM
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2022 13:38:07.9663
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 03707b74-30f3-46b6-a0e0-ff0a7438c9c4
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: baUOSCdE/RE1yAAgjxEsJrk6y6ilNL4rdqSsTNvYduIptcdDS4yiqrHbpkD9ydSZxv1Ff6otgCK5KJD7hq8bgu6cWXqiw38Cr3RZh9yVCps=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3P190MB0858
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham
        autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

There is a limitation on AC5 SoC that mmc controller
can't have DMA access over 2G memory, so use SDMA with
a bounce buffer. Swiotlb can't help because on arm64 arch
it reserves memblock's at the end of the memory.

Additionally set mask to 34 bit since on AC5 SoC RAM starts
at 0x2_00000000.

Co-developed-by: Elad Nachman <enachman@marvell.com>
Signed-off-by: Elad Nachman <enachman@marvell.com>
Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
---
v2:
   #1 Use SDMA with a bounce buffer instead of PIO.

 drivers/mmc/host/sdhci-xenon.c | 38 ++++++++++++++++++++++++++++++++++
 drivers/mmc/host/sdhci-xenon.h |  3 ++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index 08e838400b52..5f3db0425674 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -13,7 +13,9 @@
 
 #include <linux/acpi.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/ktime.h>
+#include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/pm.h>
@@ -253,6 +255,22 @@ static unsigned int xenon_get_max_clock(struct sdhci_host *host)
 		return pltfm_host->clock;
 }
 
+static int xenon_set_dma_mask(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct mmc_host *mmc = host->mmc;
+	struct device *dev = mmc_dev(mmc);
+
+	if (priv->hw_version == XENON_AC5) {
+		host->flags &= ~SDHCI_USE_64_BIT_DMA;
+
+		return dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
+	}
+
+	return sdhci_set_dma_mask(host);
+}
+
 static const struct sdhci_ops sdhci_xenon_ops = {
 	.voltage_switch		= xenon_voltage_switch,
 	.set_clock		= sdhci_set_clock,
@@ -261,6 +279,7 @@ static const struct sdhci_ops sdhci_xenon_ops = {
 	.reset			= xenon_reset,
 	.set_uhs_signaling	= xenon_set_uhs_signaling,
 	.get_max_clock		= xenon_get_max_clock,
+	.set_dma_mask		= xenon_set_dma_mask,
 };
 
 static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
@@ -486,6 +505,18 @@ static void xenon_sdhc_unprepare(struct sdhci_host *host)
 	xenon_disable_sdhc(host, sdhc_id);
 }
 
+static int xenon_ac5_probe(struct sdhci_host *host)
+{
+	struct sysinfo si;
+
+	si_meminfo(&si);
+
+	if ((si.totalram * si.mem_unit) > SZ_2G)
+		host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
+	return 0;
+}
+
 static int xenon_probe(struct platform_device *pdev)
 {
 	struct sdhci_pltfm_host *pltfm_host;
@@ -533,6 +564,12 @@ static int xenon_probe(struct platform_device *pdev)
 		}
 	}
 
+	if (priv->hw_version == XENON_AC5) {
+		err = xenon_ac5_probe(host);
+		if (err)
+			goto err_clk_axi;
+	}
+
 	err = mmc_of_parse(host->mmc);
 	if (err)
 		goto err_clk_axi;
@@ -682,6 +719,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = {
 	{ .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807},
 	{ .compatible = "marvell,armada-cp110-sdhci", .data =  (void *)XENON_CP110},
 	{ .compatible = "marvell,armada-3700-sdhci", .data =  (void *)XENON_A3700},
+	{ .compatible = "marvell,ac5-sdhci", .data = (void *)XENON_AC5},
 	{}
 };
 MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index 3e9c6c908a79..0460d97aad26 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -57,7 +57,8 @@ enum xenon_variant {
 	XENON_A3700,
 	XENON_AP806,
 	XENON_AP807,
-	XENON_CP110
+	XENON_CP110,
+	XENON_AC5
 };
 
 struct xenon_priv {
-- 
2.25.1