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Wed, 30 Nov 2022 16:11:18 +0000 Received: from BYAPR21MB1688.namprd21.prod.outlook.com ([fe80::1e50:78ec:6954:d6dd]) by BYAPR21MB1688.namprd21.prod.outlook.com ([fe80::1e50:78ec:6954:d6dd%6]) with mapi id 15.20.5880.008; Wed, 30 Nov 2022 16:11:18 +0000 From: "Michael Kelley (LINUX)" To: Borislav Petkov CC: "thomas.lendacky@amd.com" , "hpa@zytor.com" , KY Srinivasan , Haiyang Zhang , "wei.liu@kernel.org" , Dexuan Cui , "luto@kernel.org" , "peterz@infradead.org" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "lpieralisi@kernel.org" , "robh@kernel.org" , "kw@linux.com" , "bhelgaas@google.com" , "arnd@arndb.de" , "hch@infradead.org" , "m.szyprowski@samsung.com" , "robin.murphy@arm.com" , "brijesh.singh@amd.com" , "tglx@linutronix.de" , "mingo@redhat.com" , "dave.hansen@linux.intel.com" , Tianyu Lan , "kirill.shutemov@linux.intel.com" , "sathyanarayanan.kuppuswamy@linux.intel.com" , "ak@linux.intel.com" , "isaku.yamahata@intel.com" , "Williams, Dan J" , "jane.chu@oracle.com" , "seanjc@google.com" , "tony.luck@intel.com" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "linux-hyperv@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-arch@vger.kernel.org" , "iommu@lists.linux.dev" Subject: RE: [Patch v3 07/14] x86/hyperv: Change vTOM handling to use standard coco mechanisms Thread-Topic: [Patch v3 07/14] x86/hyperv: Change vTOM handling to use standard coco mechanisms Thread-Index: AQHY+es2O4adbWIH8UyWtCwRyUnUyq5JgOOAgAHDpcCAAEhFgIAAJ7oQgAjDHRCAACLagIAAALfwgAANigCAAAHQEIAAKJ+AgABUTmCAAIE5AIAAb5XAgAApEACAAXbTMA== Date: Wed, 30 Nov 2022 16:11:18 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ActionId=4d8ac474-9661-4173-b112-bd1a32d94ebd;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ContentBits=0;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Enabled=true;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Method=Standard;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Name=Internal;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SetDate=2022-11-30T16:08:38Z;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SiteId=72f988bf-86f1-41af-91ab-2d7cd011db47; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR21MB1688.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f1bed3aa-93cf-45bd-a5d8-08dad2ed839d X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Nov 2022 16:11:18.3182 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: uvGkZMQGOXQCeDBYEmXaDXbFf5hF2i90uYC/Fvp+DQd82jK/jukELL3AfibWX0njzXa69S0W/eXDNcts0wXnjO+BCrw+defhiO8J9yViFbs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR21MB3171 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Borislav Petkov Sent: Tuesday, November 29, 2022 9:47 = AM >=20 > On Tue, Nov 29, 2022 at 03:49:06PM +0000, Michael Kelley (LINUX) wrote: > > But it turns out that AMD really has two fairly different schemes: > > the C-bit scheme and the vTOM scheme. >=20 > Except it doesn't: >=20 > "In the VMSA of an SNP-active guest, the VIRTUAL_TOM field designates > a 2MB aligned guest physical address called the virtual top of memory. > When bit 1 (vTOM) of SEV_FEATURES is set in the VMSA of an SNP-active > VM, the VIRTUAL_TOM..." >=20 > So SEV_FEATURES[1] is vTOM and it is part of SNP. >=20 > Why do you keep harping on this being something else is beyond me... >=20 > I already pointed you to the patch which adds this along with the other > SEV_FEATURES. >=20 > > The details of these two AMD schemes are pretty different. vTOM is > > *not* just a minor option on the C-bit scheme. It's an either/or -- a > > guest VM is either doing the C-bit scheme or the vTOM scheme, not some > > combination. Linux code in coco/core.c could choose to treat C-bit and > > vTOM as two sub-schemes under CC_VENDOR_AMD, but that makes the code a > > bit messy because we end up with "if" statements to figure out whether > > to do things the C-bit way or the vTOM way. >=20 > Are you saying that that: >=20 > if (cc_vendor =3D=3D CC_VENDOR_AMD && > sev_features & MSR_AMD64_SNP_VTOM_ENABLED) >=20 > is messy? Why? >=20 > We will have to support vTOM sooner or later. >=20 > > Or we could model the two AMD schemes as two different vendors, > > which is what I'm suggesting. Doing so recognizes that the two schemes > > are fairly disjoint, and it makes the code cleaner. >=20 > How is that any different from the above check? >=20 > You *need* some sort of a check to differentiate between the two anyway. >=20 Alright. Enough conceptual debate. I'll do a v4 of the patch series with the AMD C-bit and vTOM schemes folder under CC_VENDOR_AMD and we can see if there's any further feedback. I should have that v4 out late= r today or tomorrow. Michael