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Date:   Wed, 30 Nov 2022 18:35:19 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Jessica Clarke <jrtc27@jrtc27.com>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Conor Dooley <conor.dooley@microchip.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Heiko Stuebner <heiko@sntech.de>,
        Andrew Jones <ajones@ventanamicro.com>,
        Guo Ren <guoren@kernel.org>, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement
 for addtional standard extensions
Message-ID: <Y4eiZ1AS+///9svR@spud>
References: <20221130180422.1642652-1-conor@kernel.org>
 <20221130180422.1642652-2-conor@kernel.org>
 <E52B0E0B-F27B-43C8-85DA-4C7AC0C52369@jrtc27.com>
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On Wed, Nov 30, 2022 at 06:29:18PM +0000, Jessica Clarke wrote:
> On 30 Nov 2022, at 18:04, Conor Dooley <conor@kernel.org> wrote:
> > 
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > The RISC-V ISA Manual allows for the first Additional Standard
> > Extension having no leading underscore. Only if there are multiple
> > Additional Standard Extensions is it needed to have an underscore.
> > 
> > The dt-binding does not validate that a multi-letter extension is
> > canonically ordered, as that'd need an even worse regex than is here,
> > but it should not fail validation for valid ISA strings.
> > 
> > Allow the first Z multi-letter extension to appear immediately prior
> > after the single-letter extensions.
> > 
> > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> > Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> > Acked-by: Guo Ren <guoren@kernel.org>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 90a7cabf58fe..e80c967a4fa4 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -80,7 +80,7 @@ properties:
> >       insensitive, letters in the riscv,isa string must be all
> >       lowercase to simplify parsing.
> >     $ref: "/schemas/types.yaml#/definitions/string"
> > -    pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
> > +    pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
> 
> Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
> 
> It certainly used to be at least; we use rv64gcxcheri...

<quote>
Non-standard extensions must be listed after all standard extensions.
They must be separated from other multi-letter extensions
by an underscore
<\quote>

Nope, you're right. I realised that the other day with the non-binding
series that was a response to v1. I had that itching feeling that I had
forgotten to do something when I was writing my changelog but could not
remember what...

Thanks Jess!