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Date:   Thu, 1 Dec 2022 09:44:12 +0000
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Subject: Re: [PATCH 2/3] arm64: tegra: Add uphy lane number and intr in p2u
 nodes
To:     Manikanta Maddireddy <mmaddireddy@nvidia.com>, vkoul@kernel.org,
        kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        thierry.reding@gmail.com, vidyas@nvidia.com
Cc:     linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
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        linux-pci@vger.kernel.org, bhelgaas@google.com,
        lpieralisi@kernel.org, nkristam@nvidia.com
References: <20221124083510.3008139-1-mmaddireddy@nvidia.com>
 <20221124083510.3008139-3-mmaddireddy@nvidia.com>
Content-Language: en-US
From:   Jon Hunter <jonathanh@nvidia.com>
In-Reply-To: <20221124083510.3008139-3-mmaddireddy@nvidia.com>
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On 24/11/2022 08:35, Manikanta Maddireddy wrote:
> UPHY lane number is required to exchange lane margin data between P2U
> and UPHY. Add uphy lane number in p2u device tree nodes.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   arch/arm64/boot/dts/nvidia/tegra234.dtsi | 120 +++++++++++++++++++++++
>   1 file changed, 120 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index eaf05ee9acd1..ec8a28a9d380 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -1109,6 +1109,11 @@ p2u_hsio_0: phy@3e00000 {
>   			reg = <0x03e00000 0x10000>;
>   			reg-names = "ctl";
>   
> +			interrupts = <0 336 0x04>;


Please use definitions and don't hard-code the values apart from the 
interrupt number.

Jon

-- 
nvpublic