Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp545210rwb; Thu, 1 Dec 2022 05:37:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf6QsPsSDKqQKiytXUioKKm07TMDyPQSnyeOGSPW4PqT4XbUTVGzpYC09BGNEdrdp1QSdkSa X-Received: by 2002:a17:907:3f8a:b0:7bf:4ae6:c36 with SMTP id hr10-20020a1709073f8a00b007bf4ae60c36mr18573122ejc.674.1669901860663; Thu, 01 Dec 2022 05:37:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669901860; cv=none; d=google.com; s=arc-20160816; b=O419LTTSNcLZlANY96Vu8kyLnoylrXkEPSHvrRoJGVFCs2GLVP+bq3lS4dr2qz35+b w+603nzE6fukWE4k0MOy21R/WXlvWBplpi1gPZr9EnEkN57yHxBobd+k3cMsmGU/orF6 Rtfsn0P0NPX0LhDleNcy072WSuLxdznY5klnrTR77BXIc76Nh3ssnme/pGVBqhdHqd7O SBLDhvT/feS+X5Kjb8EpK1Xzkkut5wga4f+dcmKvdjxReLyqiM98c8z6DsetU5Vp9nI/ 7HLUqURY5d104SbGo2owHIpUcV36S1s/+FMFhBCFkl/fwIP59HItJDM5lmQBN0FkGuwm Etmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GBh16wlKK1pVBXMjv15TuW7j92X6+xaNPp74Ke5cwzg=; b=D7V1JeRaMEYvkddC2HEkZIYnfqvjT4E+sMOWG44isjlfwe81fpvyDDbM2hSxBPxRDX SJW607WATUjkGVPU3en5bEUHbDjm+8Rikti1WcDBZ5S5RbiH2sfQbf+X5RGjFbC/tw7A V8EHIs6W/kIn1bPRsVxS8Tcunobx4ogu3/HEwsBRhTdet60ADawci7n4ZxLEKQj9LHEZ jiJU2xtXWQuv29Yqr1Ws2Rc1DGRe3vNfesCN+N26cxdpTzmKX+JDvVu2fysvMSiCD28o zBtH5FmmMxJiaHJlrMsyTSYUMkGRb3OP5UnSNU1d3XarZCn8/AHZk6UJMAT3++jQVPJH gS6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=LK0Bmkan; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sh39-20020a1709076ea700b0078ae5192906si3837261ejc.193.2022.12.01.05.37.21; Thu, 01 Dec 2022 05:37:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=LK0Bmkan; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231154AbiLANC1 (ORCPT + 82 others); Thu, 1 Dec 2022 08:02:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231149AbiLANB4 (ORCPT ); Thu, 1 Dec 2022 08:01:56 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6A9AC6E5C for ; Thu, 1 Dec 2022 05:01:55 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id k5so1774518pjo.5 for ; Thu, 01 Dec 2022 05:01:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GBh16wlKK1pVBXMjv15TuW7j92X6+xaNPp74Ke5cwzg=; b=LK0BmkanOqFOZq1Co8XQye3afavPw4jKL+JQozoXHh/ziPTUOdRmLru+J5d5ffrcuT wltWSYEDVdM0loHvjrXqktcUYCoGB566FANnIiHhdbX1kjVJ/bHCUUl9HuyKWzxFOOY6 Us/FvUSWsP/LBCrziBYyz/BBMha05zyadpOzWbzILKIDcop66dGJNvxdraxo1dYXBLfd tjcd6F7FYD4j+hDsdTXBtmXAdtJ28FHIftOqmZuC/Fwd7sS3mMPsGtPkK4ykFhlc2IeB b9HYDxtWX4eixqBZex6NvVhUM7XOVHbTuk5E4jwVmetUGHYcUupBXjoMtqvMNu1PXyb4 gN9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GBh16wlKK1pVBXMjv15TuW7j92X6+xaNPp74Ke5cwzg=; b=EfZJCwTHO2SIpaHZ1I/O6dJscmC8MRN0tboEn+0I7vXW5e4n5UoaDgYvSmjGZyYvLL VnfVF6ZqQJ1JMlcyRlvKCWE5rFEQkZltHBTXSEQf0LSpesse3C3bYWklgoVBUnFuq35g laxIQqt6VzZQKbBk909EnJEJim3zmxKqevk9zGmO8L85hpCI2abBSC/TqGpzW0isSVix BvKwOEH02BkTfOZazOnQQZg073OoI46pG6xIGn6S5wbNstJZIi+CWOpodD+8iRkR4JIn AknE1/hEiKOoDb5+5VqdMVfQbadzgURzUiDXFJrRlXGCicuw2uhlBdqaoFyp2G9EkbPS C/WQ== X-Gm-Message-State: ANoB5pmveXYQaIqNTuG7Zj65a//pJeUYe0kCoIuqrUN3O1qf6ZN/kZVL 8NnrOOe1IbUzBpeXUchhmyAmjQ== X-Received: by 2002:a17:902:d58d:b0:187:2502:888f with SMTP id k13-20020a170902d58d00b001872502888fmr52757656plh.136.1669899714535; Thu, 01 Dec 2022 05:01:54 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.81.69]) by smtp.gmail.com with ESMTPSA id l4-20020a17090a384400b00212c27abcaesm4855856pjf.17.2022.12.01.05.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 05:01:54 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra Subject: [PATCH v14 2/8] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Thu, 1 Dec 2022 18:31:29 +0530 Message-Id: <20221201130135.1115380-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221201130135.1115380-1-apatel@ventanamicro.com> References: <20221201130135.1115380-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ #include +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ #include #include +#include +#include #include #include +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node = fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 499e5f81b3fe..9066467e99e4 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { .xlate = irq_domain_xlate_onecell, }; +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -126,6 +131,8 @@ static int __init riscv_intc_init(struct device_node *node, return rc; } + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, -- 2.34.1