Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp930633rwb; Thu, 1 Dec 2022 10:04:48 -0800 (PST) X-Google-Smtp-Source: AA0mqf4rg3nEbGDbROnv3ZbMaGPhsOFbBuTLhvRfX2klsHJdGh++bdUhizGL6qouDltIEXokijTg X-Received: by 2002:a17:906:49d0:b0:79f:e0b3:3b9b with SMTP id w16-20020a17090649d000b0079fe0b33b9bmr39893155ejv.378.1669917887959; Thu, 01 Dec 2022 10:04:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669917887; cv=none; d=google.com; s=arc-20160816; b=u+7k9JUutAgbW6FHr/iZsdzGIMYd73ooDOl2Bks11+czw0kGxNYvpTOJBuSczZXtjZ /lkUrJhNzVdHiv4Kcw2gUhf/vIpWxDKsBOq4WqgxtLXNFdZc/PXrTGLrYziVkUTissfa SeWgE7P44pGHt8DDmfv7siK9PL6vtMx9LcflSZCcFDmKrNdy9QpGC8IEWCI1kvOpkvKN oRJKb63z/cmgbEZTJypoxHFejgL4bBpNTBCDxiXBdO3ytbVRI7q2GTS1mFwV1dpWVLMA yLXGIJSHjvhPYpZCX+JCGQKzcpONoWaRXkaEWx+h6XPC0AMSWXFe7mmk5W4UB6JauxGp BqLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=AQ037ja5jQIx3CrbnoE/ja8VaKfFxuNkKAls2zyW6n6Nj81z4H7t3L4seqi4Iv+bkf pYpZMWnIspuR1LAwks9SoDhCuSGst99uMuuXsQiQ1TNhavBJmA7vNbLkoDrI1TXupnEH di2X7DXRCMEQ+CyI+KgTXqKb2tEnLtaKgEhGZfsz+b3AyC44BD0ndJHJienQ6MLcdWFW KjrwRmauY8cHvwek6bnyI73JAP9fSv7Y+J576QWbWv3QbMRlkCwR0lB3/E7TBMrhDKrT iFF7um81mMrVvFF+vjnpSizNErzjcpJ4p4agXb0I0+C2Zu/icRDW4HTOrB7Gmu6wY4ti wQNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eKGYk7xy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id di5-20020a170906730500b00770872942d8si4718370ejc.958.2022.12.01.10.04.23; Thu, 01 Dec 2022 10:04:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eKGYk7xy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230287AbiLARrB (ORCPT + 82 others); Thu, 1 Dec 2022 12:47:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230126AbiLARqU (ORCPT ); Thu, 1 Dec 2022 12:46:20 -0500 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8011B8440 for ; Thu, 1 Dec 2022 09:45:25 -0800 (PST) Received: by mail-pf1-x42e.google.com with SMTP id w2so1021305pfq.12 for ; Thu, 01 Dec 2022 09:45:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=eKGYk7xyAQavSQBsjlzuDbYsvnfff8yRZnJrY1iOT7xZ147x2NChnagbYy5Bug4TEt wRJ6IWNneM9GBMiBn5Qo5XMr7ai+GLKhAnsMFjFOeYIosJheOB1X0A3+0Lr1ykOSlaow YAj3IxkYDt4xedk0ozbTm7WSErdtWYLYYuVly5BoXgI0zCgv7SmHMISwsKBTFf+IPoDR H0DH8q2yMj7s9DTyMrjp+Six+OUz2vXG4JYZ1JaODIGSBlemIVTDdLIZlarRfoGBDnSE 0DI7Fdpwmvh8xAWumCdbAX2Vn0m2X3py2bjxZwrrEjvTMDLWjTMIn6LK7qhPUj+GSTZm L9pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=ir7x7l1lShcjeLzIo4cV7uOmEssGOJPR/EOmrC5jM37tT0MxWI1niMdPrOA3Lpwpkt 5YECGjUY4cO4e/JoCtotm6DlAJGneourpUSAZ5MEyTDDTdF0KidW/jZSDAJs/YUSYwvh 45IqAuifVAeYCcO5uFRyc+Ye/xtcj0SPuYN6Ff1I5Zg3egDxB0zskY2rD4ksSu9SMEJ7 KlwnVscEbaRnZ3y+4WqMuleYzzVj8jsHN1yYWUpsDT5Vn2O2lQx8qeXwHNsddtpZzpFV JTDr32zkd6bqgzMuA2hfLI73cdSQXhKqESqz6wMOnLO6DaGNC8fMeYDf5il6Ssg1pPXX R3uQ== X-Gm-Message-State: ANoB5pmM3x4LDyEdYVVoOxRT0QNc//0dORtisAbVktZhFi2z6HSYhXOf cYyK45QlV/oqUPuxQuhlFz54 X-Received: by 2002:a65:5781:0:b0:470:1b:f65c with SMTP id b1-20020a655781000000b00470001bf65cmr52099444pgr.199.1669916725285; Thu, 01 Dec 2022 09:45:25 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:45:24 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 15/23] scsi: ufs: ufs-qcom: Use bitfields where appropriate Date: Thu, 1 Dec 2022 23:13:20 +0530 Message-Id: <20221201174328.870152-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use bitfield macros where appropriate to simplify the driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 44466a395bb5..9d96ac71b27f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -17,12 +17,9 @@ #define DEFAULT_CLK_RATE_HZ 1000000 #define BUS_VECTOR_NAME_LEN 32 -#define UFS_HW_VER_MAJOR_SHFT (28) -#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) -#define UFS_HW_VER_MINOR_SHFT (16) -#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) -#define UFS_HW_VER_STEP_SHFT (0) -#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) +#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) +#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) +#define UFS_HW_VER_STEP_MASK GENMASK(15, 0) /* vendor specific pre-defined parameters */ #define SLOW 1 @@ -76,24 +73,28 @@ enum { #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) /* bit definitions for REG_UFS_CFG1 register */ -#define QUNIPRO_SEL 0x1 -#define UTP_DBG_RAMS_EN 0x20000 +#define QUNIPRO_SEL BIT(0) +#define UFS_PHY_SOFT_RESET BIT(1) +#define UTP_DBG_RAMS_EN BIT(17) #define TEST_BUS_EN BIT(18) #define TEST_BUS_SEL GENMASK(22, 19) #define UFS_REG_TEST_BUS_EN BIT(30) +#define UFS_PHY_RESET_ENABLE 1 +#define UFS_PHY_RESET_DISABLE 0 + /* bit definitions for REG_UFS_CFG2 register */ -#define UAWM_HW_CGC_EN (1 << 0) -#define UARM_HW_CGC_EN (1 << 1) -#define TXUC_HW_CGC_EN (1 << 2) -#define RXUC_HW_CGC_EN (1 << 3) -#define DFC_HW_CGC_EN (1 << 4) -#define TRLUT_HW_CGC_EN (1 << 5) -#define TMRLUT_HW_CGC_EN (1 << 6) -#define OCSC_HW_CGC_EN (1 << 7) +#define UAWM_HW_CGC_EN BIT(0) +#define UARM_HW_CGC_EN BIT(1) +#define TXUC_HW_CGC_EN BIT(2) +#define RXUC_HW_CGC_EN BIT(3) +#define DFC_HW_CGC_EN BIT(4) +#define TRLUT_HW_CGC_EN BIT(5) +#define TMRLUT_HW_CGC_EN BIT(6) +#define OCSC_HW_CGC_EN BIT(7) /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ -#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */ +#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ @@ -101,17 +102,11 @@ enum { TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) /* bit offset */ -enum { - OFFSET_UFS_PHY_SOFT_RESET = 1, - OFFSET_CLK_NS_REG = 10, -}; +#define OFFSET_CLK_NS_REG 0xa /* bit masks */ -enum { - MASK_UFS_PHY_SOFT_RESET = 0x2, - MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF, - MASK_CLK_NS_REG = 0xFFFC00, -}; +#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) +#define MASK_CLK_NS_REG GENMASK(23, 10) /* QCOM UFS debug print bit mask */ #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) @@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, { u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); - *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT; - *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT; - *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT; + *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); + *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); + *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); }; static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE), + REG_UFS_CFG1); /* * Make sure assertion of ufs phy reset is written to @@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE), + REG_UFS_CFG1); /* * Make sure de-assertion of ufs phy reset is written to -- 2.25.1