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From:   Bjorn Andersson <andersson@kernel.org>
To:     krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
        sboyd@kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>,
        abel.vesa@linaro.org, agross@kernel.org, mturquette@baylibre.com
Cc:     linux-arm-msm@vger.kernel.org,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: (subset) [PATCH v4 0/9] clk: qcom: Add support for SM8550
Date:   Fri,  2 Dec 2022 14:58:39 -0600
Message-Id: <167001472430.2721945.18371070491439646319.b4-ty@kernel.org>
In-Reply-To: <20221130112852.2977816-1-abel.vesa@linaro.org>
References: <20221130112852.2977816-1-abel.vesa@linaro.org>
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On Wed, 30 Nov 2022 13:28:43 +0200, Abel Vesa wrote:
> This patchset adds clock support for the Qualcomm SM8550 SoC,
> It adds support for the new type of PLL, the TCSR clock controller
> driver, support for configurable poll timeout, the RPMh clocks
> and the bindings.
> 
> Changes since v3:
>  * Dropped the GDSC configurable poll timeout patch, like Stephen
>    suggested
>  * Added Krzysztof's R-b tag to TCSRCC and GCC binding patches
> 
> [...]

Applied, thanks!

[1/9] dt-bindings: clock: Add SM8550 GCC clocks
      commit: 47ba9c50bbeb1c5005eb06ca0a2ab92604a54b62
[3/9] clk: qcom: gdsc: Increase status poll timeout
      commit: 7364379d725fc8240a90190dc9da662ada43d9d1
[4/9] clk: qcom: Add LUCID_OLE PLL type for SM8550
      commit: 1de7e70941fff80139df8a37d4b35264543e3fc0
[5/9] clk: qcom: Add GCC driver for SM8550
      commit: 955f2ea3b9e94d0fa20ce3a78ef3063923d41b58

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>