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Sat, 3 Dec 2022 02:54:53 +0000 Date: Sat, 3 Dec 2022 10:51:48 +0800 From: Feng Tang To: "Paul E. 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McKenney wrote: [...] > > > > > > > (My next step involves a pillow, but will follow up tomorrow morning > > > > > > > Pacific Time.) > > > > > > > > > > > > Really thanks for checking this through late night! > > > > > > > > > > No problem, and I guess it is instead the day after tomorrow, but > > > > > I thought you might be interested in chronyd's opinion: > > > > > > > > > > [root@rtptest1029.snc8 ~]# cat /var/lib/chrony/drift > > > > >         40001.074911             0.002098 > > > > > > > > > > In contrast, on my Fedora laptop: > > > > > > > > > > $ sudo cat /var/lib/chrony/drift > > > > >             2.074313             0.186606 > > > > > > > > > > I am (perhaps incorrectly) taking this to indicate that TSC is in fact > > > > > drifting with respect to standard time. > > > > > > > > This info is very useful! It further confirms the CPUID(0x15) gave > > > > the wrong frequency info. > > > > > > So the TSC is just doing what it is told. ;-) > > > > > > This indicates a firmware problem? > > > > > > > Also I don't think TSC itself is drifting, and the drift some from > > > > the wrong match calculation(1896 MHz), if we give it the correct > > > > number (likely 1975 MHz here), there shouldn't be big chrony drift > > > > like your Fedora laptop. > > > > > > Resetting so that the clocksource watchdog once again gets rid of TSC, > > > but leaving nohpet: > > > > > > [    0.000000] tsc: using CPUID[0x15] crystal_khz= 24000 kHz ebx=158 eax=2 > > > [    0.000000] tsc: Detected 1900.000 MHz processor > > > [    0.000000] tsc: Detected 1896.000 MHz TSC > > > [    5.287750] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns > > > [   17.963947] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x36a8d32ce31, max_idle_ns: 881590731004 ns > > > [   19.996287] clocksource: timekeeping watchdog on CPU3: Marking clocksource 'tsc-early' as unstable because the skew is too large: > > > [   20.040287] clocksource:                       'refined-jiffies' wd_nsec: 503923392 wd_now: fffb73f8 wd_last: fffb7200 mask: ffffffff > > > [   20.067286] clocksource:                       'tsc-early' cs_nsec: 588021368 cs_now: 581c1eb378 cs_last: 57d9aad9e8 mask: ffffffffffffffff > > >  [   20.096286] clocksource:                       No current clocksource. > > >  [   20.111286] tsc: Marking TSC unstable due to clocksource watchdog > > >  [   24.582541] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns > > >  [   49.739301] clocksource: Switched to clocksource refined-jiffies > > >  [   50.046356] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns > > >  [   50.066475] clocksource: Switched to clocksource acpi_pm > > > > > > # cat /var/lib/chrony/drift  > > >             1.372570             0.020049 > > > > > > I interpret this to mean that acpi_pm (and thus from prior observations, > > > HPET as well) are counting at the correct rate. > > > > Correct. And this is a good news! that 1975 MHz seems to be the right > > number. > > > > Could you try below patch, it should override the CPUID calculation > > and forced to use HW timer calibrated number: > > > > --- > > diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c > > index a78e73da4a74..68a2fea4961d 100644 > > --- a/arch/x86/kernel/tsc.c > > +++ b/arch/x86/kernel/tsc.c > > @@ -1417,7 +1417,8 @@ static int __init init_tsc_clocksource(void) > > * When TSC frequency is known (retrieved via MSR or CPUID), we skip > > * the refined calibration and directly register it as a clocksource. > > */ > > - if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { > > +// if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { > > + if (false) { > > if (boot_cpu_has(X86_FEATURE_ART)) > > art_related_clocksource = &clocksource_tsc; > > clocksource_register_khz(&clocksource_tsc, tsc_khz); > > --- > > > > And together with b50db7095fe0 "x86/tsc: Disable clocksource watchdog > > for TSC on qualified platorms". I assume this will tell TSC to use > > 1975 MHZ as its frequency. > > This did not change things, Maybe the kernel is with the tsc reclibrate patch? it will not use the reclibrated frequency for a KNOWN_FREQ case, but just print out the info. Anyway this doesn't matter, as it's just for debug, and your way already proved the 1975 MHz is the right number :) > but when I hardcoded tsc_khz to 1975, the > clocksource watchdog no longer disables TSC and chrony shows drifts of > less than 2.0. (As opposed to about 40,000 without the hardcoding.) > > So yes, forcing 1975 makes TSC work nicely. Yay! ;-) Great to know it works and we have some workaround before a final solution :) Thanks, Feng > Thanx, Paul