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From:   Chukun Pan <amadeus@jmu.edu.cn>
To:     heiko@sntech.de
Cc:     alexandre.torgue@foss.st.com, amadeus@jmu.edu.cn,
        davem@davemloft.net, david.wu@rock-chips.com,
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        krzysztof.kozlowski@linaro.org, kuba@kernel.org,
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Subject: Re: Re: [PATCH 1/2] dt-bindings: net: rockchip-dwmac: add rk3568 xpcs compatible
Date:   Sat,  3 Dec 2022 17:00:15 +0800
Message-Id: <20221203090015.16132-1-amadeus@jmu.edu.cn>
In-Reply-To: <3689593.Mh6RI2rZIc@diego>
References: <3689593.Mh6RI2rZIc@diego>
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Precedence: bulk

> Actually looking deeper in the TRM, having these registers "just" written
> to from the dwmac-glue-layer feels quite a bit like a hack.

> The "pcs" thingy referenced in patch2 actually looks more like a real device
> with its own section in the TRM and own iomem area. This pcs device then
> itself has some more settings stored in said pipe-grf.

> So this looks more like it wants to be an actual phy-driver.

> @Chukun Pan: plase take a look at something like
> https://elixir.bootlin.com/linux/latest/source/drivers/phy/mscc/phy-ocelot-serdes.c#L398
> on how phy-drivers for ethernets could look like.

> Aquiring such a phy from the dwmac-glue and calling phy_set_mode after
> moving the xpcs_setup to a phy-driver shouldn't be too hard I think.

Thanks for pointing that out.
The patch2 is come from the sdk kernel of rockchip.
The sgmii-phy of RK3568 is designed on nanning combo phy.
In the sdk kernel, if we want to use sgmii mode, we need
to modify the device tree in the gmac section like this:

```
&gmac0 {
	power-domains = <&power RK3568_PD_PIPE>;
	phys = <&combphy1_usq PHY_TYPE_SGMII>;
	phy-handle = <&sgmii_phy>;
	phy-mode = "sgmii";
	rockchip,pipegrf = <&pipegrf>;
	rockchip,xpcs = <&xpcs>;
	status = "okay";
};
```

I'm not sure how to write this on the mainline kernel.
Any hint will be appreciated.

--
Thanks,
Chukun

-- 
2.25.1