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Date:   Sun, 04 Dec 2022 13:10:19 +0100
From:   "Arnd Bergmann" <arnd@arndb.de>
To:     "Dmitry Torokhov" <dmitry.torokhov@gmail.com>, soc@kernel.org
Cc:     "Li Yang" <leoyang.li@nxp.com>, "Qiang Zhao" <qiang.zhao@nxp.com>,
        "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
        "Linus Walleij" <linus.walleij@linaro.org>,
        "Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
        linuxppc-dev@lists.ozlabs.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-usb@vger.kernel.org
Subject: Re: [RESEND PATCH] soc: fsl: qe: request pins non-exclusively
Content-Type: text/plain
Precedence: bulk

On Sun, Dec 4, 2022, at 05:50, Dmitry Torokhov wrote:
>
> SoC team, the problematic patch has been in next for a while and it
> would be great to get the fix in to make sure the driver is not broken
> in 6.2. Thanks!

I have no problem taking thsi patch, but I get a merge conflict that
I'm not sure how to resolve:


@@@ -186,23 -182,27 +180,43 @@@ struct qe_pin *qe_pin_request(struct de
        if (WARN_ON(!gc)) {
                err = -ENODEV;
                goto err0;
++<<<<<<< HEAD
 +      }
 +      qe_pin->gpiod = gpiod;
 +      qe_pin->controller = gpiochip_get_data(gc);
 +      /*
 +       * FIXME: this gets the local offset on the gpio_chip so that the driver
 +       * can manipulate pin control settings through its custom API. The real
 +       * solution is to create a real pin control driver for this.
 +       */
 +      qe_pin->num = gpio_chip_hwgpio(gpiod);
 +
 +      if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
 +              pr_debug("%s: tried to get a non-qe pin\n", __func__);
 +              gpiod_put(gpiod);
++=======
+       } else if (!fwnode_device_is_compatible(gc->fwnode,
+                                               "fsl,mpc8323-qe-pario-bank")) {
+               dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__);
++>>>>>>> soc: fsl: qe: request pins non-exclusively
                err = -EINVAL;
-               goto err0;
+       } else {
+               qe_pin->controller = gpiochip_get_data(gc);
+               /*
+                * FIXME: this gets the local offset on the gpio_chip so that
+                * the driver can manipulate pin control settings through its
+                * custom API. The real solution is to create a real pin control
+                * driver for this.
+                */
+               qe_pin->num = desc_to_gpio(gpiod) - gc->base;
        }

Could you rebase the patch on top of the soc/driver branch in the
soc tree and send the updated version?

       Arnd