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Message-ID: <f5a07ab14341d3a7ce8faf38f1d603eb4aed3c7b.camel@icenowy.me>
Subject: Re: [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and
 Dock devicetree
From:   Icenowy Zheng <uwu@icenowy.me>
To:     Samuel Holland <samuel@sholland.org>,
        Jisheng Zhang <jszhang@kernel.org>
Cc:     linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
        Rob Herring <robh+dt@kernel.org>,
        Conor Dooley <conor@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>,
        Ilpo =?ISO-8859-1?Q?J=E4rvinen?= <ilpo.jarvinen@linux.intel.com>
Date:   Mon, 05 Dec 2022 16:15:46 +0800
In-Reply-To: <91d7eebd-7433-c06d-6d14-a01d11af9df9@sholland.org>
References: <20221127132448.4034-1-jszhang@kernel.org>
         <20221127132448.4034-8-jszhang@kernel.org>
         <91d7eebd-7433-c06d-6d14-a01d11af9df9@sholland.org>
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=E5=9C=A8 2022-11-30=E6=98=9F=E6=9C=9F=E4=B8=89=E7=9A=84 01:25 -0600=EF=BC=
=8CSamuel Holland=E5=86=99=E9=81=93=EF=BC=9A
> On 11/27/22 07:24, Jisheng Zhang wrote:
> > Sipeed manufactures a M1s system-on-module and dock board, add
> > basic
> > support for them.
> >=20
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> > =C2=A0arch/riscv/boot/dts/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 =
1 +
> > =C2=A0arch/riscv/boot/dts/bouffalolab/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 |=C2=A0 2 ++
> > =C2=A0.../dts/bouffalolab/bl808-sipeed-m1s-dock.dts | 25
> > +++++++++++++++++++
> > =C2=A0.../dts/bouffalolab/bl808-sipeed-m1s.dtsi=C2=A0=C2=A0=C2=A0=C2=A0=
 | 21
> > ++++++++++++++++
> > =C2=A04 files changed, 49 insertions(+)
> > =C2=A0create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile
> > =C2=A0create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-
> > m1s-dock.dts
> > =C2=A0create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-
> > m1s.dtsi
> >=20
> > diff --git a/arch/riscv/boot/dts/Makefile
> > b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b525467152b2 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,4 +1,5 @@
> > =C2=A0# SPDX-License-Identifier: GPL-2.0
> > +subdir-y +=3D bouffalolab
> > =C2=A0subdir-y +=3D sifive
> > =C2=A0subdir-y +=3D starfive
> > =C2=A0subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) +=3D canaan
> > diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile
> > b/arch/riscv/boot/dts/bouffalolab/Makefile
> > new file mode 100644
> > index 000000000000..5419964e892d
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_BOUFFALOLAB) +=3D bl808-sipeed-m1s-dock.dtb
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-
> > dock.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-
> > dock.dts
> > new file mode 100644
> > index 000000000000..c6b4894a7b88
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
> > @@ -0,0 +1,25 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "bl808-sipeed-m1s.dtsi"
> > +
> > +/ {
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0model =3D "Sipeed M1s Dock";
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0compatible =3D "sipeed,m1s-d=
ock", "sipeed,m1s",
> > "bouffalolab,bl808";
> > +
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0aliases {
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0serial0 =3D &uart0;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0};
> > +
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0chosen {
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0stdout-path =3D "serial0:2000000n8";
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0};
> > +};
> > +
> > +&uart0 {
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0status =3D "okay";
> > +};
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> > b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> > new file mode 100644
> > index 000000000000..5026de768534
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "bl808.dtsi"
> > +
> > +/ {
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0compatible =3D "sipeed,m1s",=
 "bouffalolab,bl808";
> > +
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0memory@50000000 {
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0device_type =3D "memory";
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0reg =3D <0x50000000 0x04000000>;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0};
>=20
> The PSRAM is part of the BL808, so this should go in the SoC .dtsi
> file.
> (Unless I'm missing something and there are BL808 variants with
> different amounts of memory. The PSRAM init code in the SDK does size
> detection, so I suppose it is possible.)

I think it really has variants.

>=20
> Regards,
> Samuel
>=20
> > +};
> > +
> > +&xtal {
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0clock-frequency =3D <4000000=
0>;
> > +};
>=20
>=20
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