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From:   Vadym Kochan <vadym.kochan@plvision.eu>
To:     Hu Ziji <huziji@marvell.com>, Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Elad Nachman <enachman@marvell.com>,
        Chris Packham <chris.packham@alliedtelesis.co.nz>,
        Vadym Kochan <vadym.kochan@plvision.eu>
Subject: [PATCH v3 0/3] mmc: xenon: Fix 2G DMA limitation on AC5 SoC
Date:   Mon,  5 Dec 2022 12:59:27 +0200
Message-Id: <20221205105931.410686-1-vadym.kochan@plvision.eu>
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There is a limitation on AC5 SoC that mmc controller
can't have DMA access over 2G memory, so use SDMA with
a bounce buffer. Swiotlb can't help because on arm64 arch
it reserves memblock's at the end of the memory.

Additionally set mask to 34 bit since on AC5 SoC RAM starts
at 0x2_00000000.

Also add compatible string for AC5 SoC.

v3:
   #1 Fix missing EXPORT_SYMBOL_GPL for sdhci_set_dma_mask

   #2 Put compatible string in alphabetical order in the yaml file

v2:
   #1 Add compatible string for dt-bindings

   #2 Use SDMA with a bounce buffer instead of PIO.

Vadym Kochan (3):
  dt-bindings: mmc: xenon: Add compatible string for AC5 SoC
  mmc: sdhci: Export sdhci_set_dma_mask to be used by the drivers
  mmc: xenon: Fix 2G limitation on AC5 SoC

 .../bindings/mmc/marvell,xenon-sdhci.yaml     |  1 +
 drivers/mmc/host/sdhci-xenon.c                | 38 +++++++++++++++++++
 drivers/mmc/host/sdhci-xenon.h                |  3 +-
 drivers/mmc/host/sdhci.c                      |  3 +-
 drivers/mmc/host/sdhci.h                      |  2 +
 5 files changed, 45 insertions(+), 2 deletions(-)

-- 
2.25.1