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Date:   Tue, 06 Dec 2022 00:51:42 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        martin.petersen@oracle.com, jejb@linux.ibm.com,
        andersson@kernel.org, vkoul@kernel.org
CC:     quic_cang@quicinc.com, quic_asutoshd@quicinc.com,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org,
        ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com,
        avri.altman@wdc.com, bvanassche@acm.org
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v4_04/23=5D_phy=3A_qcom-qmp-ufs=3A_Add_s?= =?US-ASCII?Q?upport_for_configuring_PHY_in_HS_Series_B_mode?=
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On 1 December 2022 20:43:09 GMT+03:00, Manivannan Sadhasivam <manivannan=
=2Esadhasivam@linaro=2Eorg> wrote:
>Add separate tables_hs_b instance to allow the PHY driver to configure th=
e
>PHY in HS Series B mode=2E The individual SoC configs need to supply the
>serdes register setting in tables_hs_b and the UFS driver can request the
>Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_=
B=2E
>
>Reviewed-by: Dmitry Baryshkov <dmitry=2Ebaryshkov@linaro=2Eorg>
>Signed-off-by: Manivannan Sadhasivam <manivannan=2Esadhasivam@linaro=2Eor=
g>
>---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec b/drivers/phy/qual=
comm/phy-qcom-qmp-ufs=2Ec
>index 516027e356f0=2E=2E2d5dd336aeb2 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec
>@@ -547,6 +547,8 @@ struct qmp_phy_cfg {
>=20
> 	/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
> 	const struct qmp_phy_cfg_tbls tbls;
>+	/* Additional sequence for HS Series B */
>+	const struct qmp_phy_cfg_tbls tbls_hs_b;
>=20
> 	/* clock ids to be requested */
> 	const char * const *clk_list;
>@@ -580,6 +582,7 @@ struct qmp_ufs {
> 	struct reset_control *ufs_reset;
>=20
> 	struct phy *phy;
>+	u32 mode;
> };
>=20
> static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
>@@ -841,6 +844,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, con=
st struct qmp_phy_cfg_tbls
> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp=
_phy_cfg *cfg)
> {
> 	qmp_ufs_serdes_init(qmp, &cfg->tbls);
>+	if (qmp->mode =3D=3D PHY_MODE_UFS_HS_B)
>+		qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);

I still think that qmp_ufs_init_registers() is a way to go here , see the =
pcie driver=2E

> 	qmp_ufs_lanes_init(qmp, &cfg->tbls);
> 	qmp_ufs_pcs_init(qmp, &cfg->tbls);
> }
>@@ -1011,9 +1016,19 @@ static int qmp_ufs_disable(struct phy *phy)
> 	return qmp_ufs_exit(phy);
> }
>=20
>+static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int sub=
mode)
>+{
>+	struct qmp_ufs *qmp =3D phy_get_drvdata(phy);
>+
>+	qmp->mode =3D mode;
>+
>+	return 0;
>+}
>+
> static const struct phy_ops qcom_qmp_ufs_phy_ops =3D {
> 	=2Epower_on	=3D qmp_ufs_enable,
> 	=2Epower_off	=3D qmp_ufs_disable,
>+	=2Eset_mode	=3D qmp_ufs_set_mode,
> 	=2Eowner		=3D THIS_MODULE,
> };
>=20

--=20
With best wishes
Dmitry