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charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1 December 2022 20:43:16 GMT+03:00, Manivannan Sadhasivam wrote: >UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init >sequence is compatible with SM8350=2E Hence, add the tbls_hs_g4 instance >reusing the G4 init sequence of SM8350=2E Reviewed-by: Dmitry Baryshkov > >Signed-off-by: Manivannan Sadhasivam >--- > drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec | 8 ++++++++ > 1 file changed, 8 insertions(+) > >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec b/drivers/phy/qual= comm/phy-qcom-qmp-ufs=2Ec >index 75e55c4181c9=2E=2E96e03d4249da 100644 >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec >@@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = =3D { > =2Eserdes =3D sm8350_ufsphy_hs_b_serdes, > =2Eserdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), > }, >+ =2Etbls_hs_g4 =3D { >+ =2Etx =3D sm8350_ufsphy_g4_tx, >+ =2Etx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), >+ =2Erx =3D sm8350_ufsphy_g4_rx, >+ =2Erx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), >+ =2Epcs =3D sm8350_ufsphy_g4_pcs, >+ =2Epcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), >+ }, > =2Eclk_list =3D sm8450_ufs_phy_clk_l, > =2Enum_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), > =2Evreg_list =3D qmp_phy_vreg_l, --=20 With best wishes Dmitry