Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Mon, 5 Dec 2022 15:52:53 -0600
From:   Bjorn Andersson <andersson@kernel.org>
To:     Robert Marko <robimarko@gmail.com>
Cc:     agross@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        mani@kernel.org, lpieralisi@kernel.org, kw@linux.com,
        svarbanov@mm-sol.com, shawn.guo@linaro.org,
        linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY
Message-ID: <20221205215253.itobukkyiecn7xi7@builder.lan>
References: <20221116214841.1116735-1-robimarko@gmail.com>
 <20221116214841.1116735-2-robimarko@gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20221116214841.1116735-2-robimarko@gmail.com>
Precedence: bulk

On Wed, Nov 16, 2022 at 10:48:34PM +0100, Robert Marko wrote:
> IPQ8074 comes in 2 silicon versions:
> * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> 
> v2 is the final and production version that is actually supported by the
> kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> 
> Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
> by fixing the Gen3 QMP PHY node first.
> 
> Change the compatible to the Gen3 QMP PHY, correct the register space start
> and size, add the missing misc PCS register space.
> 

Does this imply that the current node doesn't actually work?

If that's the case, could we perhaps adopt Johan Hovolds' new binding
and drop the subnode in favor of just a flat reg covering the whole
QMP region?

Regards,
Bjorn

> Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 6649a758d8df..9503dfb25d50 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 {
>  			status = "disabled";
>  		};
>  
> -		pcie_qmp0: phy@86000 {
> -			compatible = "qcom,ipq8074-qmp-pcie-phy";
> -			reg = <0x00086000 0x1c4>;
> +		pcie_qmp0: phy@84000 {
> +			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
> +			reg = <0x00084000 0x1bc>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> @@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 {
>  				      "common";
>  			status = "disabled";
>  
> -			pcie_phy0: phy@86200 {
> -				reg = <0x86200 0x16c>,
> -				      <0x86400 0x200>,
> -				      <0x86800 0x4f4>;
> +			pcie_phy0: phy@84200 {
> +				reg = <0x84200 0x16c>,
> +				      <0x84400 0x200>,
> +				      <0x84800 0x1f0>,
> +				      <0x84c00 0xf4>;
>  				#phy-cells = <0>;
>  				#clock-cells = <0>;
>  				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> -- 
> 2.38.1
>