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Message-ID: <7117060e-9081-2bb2-823b-a1a311c8cb72@kernel.org>
Date:   Tue, 6 Dec 2022 07:52:13 +0100
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Subject: Re: [PATCH v3 1/2] earlycon: Let users set the clock frequency
Content-Language: en-US
To:     Ricardo Ribalda <ribalda@chromium.org>,
        Jonathan Corbet <corbet@lwn.net>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc:     linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-serial@vger.kernel.org
References: <20221123-serial-clk-v3-0-49c516980ae0@chromium.org>
 <20221123-serial-clk-v3-1-49c516980ae0@chromium.org>
From:   Jiri Slaby <jirislaby@kernel.org>
In-Reply-To: <20221123-serial-clk-v3-1-49c516980ae0@chromium.org>
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On 24. 11. 22, 13:39, Ricardo Ribalda wrote:
> Some platforms, namely AMD Picasso, use non standard uart clocks (48M),
> witch makes it impossible to use with earlycon.
> 
> Let the user select its own frequency.
> 
> Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>

Reviewed-by: Jiri Slaby <jirislaby@kernel.org>

> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index a465d5242774..9efb6c3b0486 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -1182,10 +1182,10 @@
>   			specified, the serial port must already be setup and
>   			configured.
>   
> -		uart[8250],io,<addr>[,options]
> -		uart[8250],mmio,<addr>[,options]
> -		uart[8250],mmio32,<addr>[,options]
> -		uart[8250],mmio32be,<addr>[,options]
> +		uart[8250],io,<addr>[,options[,uartclk]]
> +		uart[8250],mmio,<addr>[,options[,uartclk]]
> +		uart[8250],mmio32,<addr>[,options[,uartclk]]
> +		uart[8250],mmio32be,<addr>[,options[,uartclk]]
>   		uart[8250],0x<addr>[,options]
>   			Start an early, polled-mode console on the 8250/16550
>   			UART at the specified I/O port or MMIO address.
> @@ -1194,7 +1194,9 @@
>   			If none of [io|mmio|mmio32|mmio32be], <addr> is assumed
>   			to be equivalent to 'mmio'. 'options' are specified
>   			in the same format described for "console=ttyS<n>"; if
> -			unspecified, the h/w is not initialized.
> +			unspecified, the h/w is not initialized. 'uartclk' is
> +			the uart clock frequency; if unspecified, it is set
> +			to 'BASE_BAUD' * 16.
>   
>   		pl011,<addr>
>   		pl011,mmio32,<addr>
> diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
> index a5f380584cda..3a0c88419b6c 100644
> --- a/drivers/tty/serial/earlycon.c
> +++ b/drivers/tty/serial/earlycon.c
> @@ -120,7 +120,13 @@ static int __init parse_options(struct earlycon_device *device, char *options)
>   	}
>   
>   	if (options) {
> +		char *uartclk;
> +
>   		device->baud = simple_strtoul(options, NULL, 0);
> +		uartclk = strchr(options, ',');
> +		if (uartclk && kstrtouint(uartclk + 1, 0, &port->uartclk) < 0)
> +			pr_warn("[%s] unsupported earlycon uart clkrate option\n",
> +				options);
>   		length = min(strcspn(options, " ") + 1,
>   			     (size_t)(sizeof(device->options)));
>   		strscpy(device->options, options, length);
> @@ -139,7 +145,8 @@ static int __init register_earlycon(char *buf, const struct earlycon_id *match)
>   		buf = NULL;
>   
>   	spin_lock_init(&port->lock);
> -	port->uartclk = BASE_BAUD * 16;
> +	if (!port->uartclk)
> +		port->uartclk = BASE_BAUD * 16;
>   	if (port->mapbase)
>   		port->membase = earlycon_map(port->mapbase, 64);
>   
> 

-- 
js
suse labs