Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp7409278rwb; Tue, 6 Dec 2022 05:32:28 -0800 (PST) X-Google-Smtp-Source: AA0mqf70h03mLBUNHmFxr+o3TBv6cgSf5LZSb3GogrsRfy/h2N6AYzG2Q5rB38vyvBY5Ow+Cqq43 X-Received: by 2002:a17:907:cf84:b0:78d:4795:ff1f with SMTP id ux4-20020a170907cf8400b0078d4795ff1fmr27719010ejc.331.1670333548035; Tue, 06 Dec 2022 05:32:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670333548; cv=none; d=google.com; s=arc-20160816; b=zi035grzb54EXj4mcBToOLXTwNGU9u9NPHY7z6WnvYASpKdDHmMniua92W0Gb23dEl /MZU50hRrM1M74yab8WVuaeY/I42z3uAXkqp4GSMZBmrjgDZQyCSBao0u+rUKSCp72l7 WVoUQTrvAQbKmbrCKi02kiF9dj+rBZbxXmcYNrkS+pv3aC5sca0SnSm+eps94y4HgcHz Y/lpppSqhEKPAcNkc1h05EBSkYeYv2LnDr6Q0EaYFOqnF9fj6P2ByHyYvOkch/ACq2TF /HtLAJRG7cT2BhjEDM5AIAW2dTjFHhiv9x6nmz70Uji2ZOwp3VB/W87FqwDi7dohSzRX bYNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HyTsVNX7Hzgy2yuFXUB0FPuyNnjByEWV/KA5BFtfNhA=; b=hddVGs1qRjERSNWwsZ5vyJNMQ2mIapyc0O8ryZVgIQWPgU6cKQuv7W4omAbHOI6fr2 BeQGjmgTXbVApH5zUHIUqfeEaF5bB2bku8iNMFMi3M888mdJtBmm1YpMA8EhiOe/A4ts XAFJjR37trLOiiJQ256XSACHCXyR6e7JzbLr6cnkKvjKATCy8B/mc97kmoqSj6jCuxU5 m1OPGv6GegKxGKDsGTnrvfoW9jb1ryZSEtSJCxgwheLIc0FpMXf3mPnlO4B9wfDwycR4 kKw14GdmDhAO4cews3nypl2Lz7x5TfB2/AFgdcCk2ZVuxsAbdUTHxegkx1flW9wuzc0G RE0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Qd/GL1MH"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s15-20020a056402014f00b0046b953601besi1807517edu.29.2022.12.06.05.32.08; Tue, 06 Dec 2022 05:32:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Qd/GL1MH"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234804AbiLFM5C (ORCPT + 79 others); Tue, 6 Dec 2022 07:57:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234724AbiLFM4v (ORCPT ); Tue, 6 Dec 2022 07:56:51 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BF7A26AE5 for ; Tue, 6 Dec 2022 04:56:43 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id n21so5911916ejb.9 for ; Tue, 06 Dec 2022 04:56:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HyTsVNX7Hzgy2yuFXUB0FPuyNnjByEWV/KA5BFtfNhA=; b=Qd/GL1MHeXgLbMYyUrp+KBSyKHgcTmuslNeiJrh5b+znPB3XYt63cr/RFYF+WuF7rZ OEHIlFQ69Ace+DlLbnFut+BIZEqRWKnZmMEz9bmMWf3256ta1OlfM+lHa7apP0mi5wzO Tsm6MHmFHRnH4mjAJbKkX/7m8wsxAoWAVCEdua69zcgLjsSeFafVJJp1RZPZhy9qkBPJ kkgf3ydJjFpeeYFgObKDZrcC5RHeQYIxzuHMgJ7xnMvCUhdvzpf6uXK9yWPcrsyxoMIb m47WvKOCFwIWUN6NFZYt9mA5j0RglquttEcdDKT9D5wKpU7kfjO3V+39MB1wIAtAIumB CjVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HyTsVNX7Hzgy2yuFXUB0FPuyNnjByEWV/KA5BFtfNhA=; b=SzdVkHssznQfHW5w+4YW4VvbwSLE5rIYR8o/JMrqaQ/HrVcStwiGxlp1MIFo7o4qxK 8GEVe6briSMFxSpWGEQIXPu1/qhTen3d7VQEdy7TpYhyZsGF5zZONU6BABBPzBTq98Mh HjqzwsTosO4DfYAcwQ7bXvqxIojpTH8udl+o7Snel2PDFqK6Y/BYNNanOQ82cCGVLS7t 39z3NTSyXBtC1ZCgkmaGM1KWwJEYnWkhNQb9Yl8Mws8Qt/HqtWdOdSMKSi1/C2hj31dm XZsa56F1eid9J/xcj/BT/dW33daySw6fLdpFwwasKyIV4H13Or2ST5gpHAMZqGFVK2Lb Mc2A== X-Gm-Message-State: ANoB5pnG8uwf/VRt+80nhcgOUg02CEviotUGIuQ85JCWisjBqMvqjPiy LblGVRoI7qcenFpQBgyjJwhFJQ== X-Received: by 2002:a17:906:1484:b0:7ae:6746:f270 with SMTP id x4-20020a170906148400b007ae6746f270mr23036100ejc.728.1670331401625; Tue, 06 Dec 2022 04:56:41 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id v15-20020aa7cd4f000000b0046150ee13besm932991edw.65.2022.12.06.04.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 04:56:41 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 1/5] dt-bindings: clock: Add SM8550 TCSR CC clocks Date: Tue, 6 Dec 2022 14:56:31 +0200 Message-Id: <20221206125635.952114-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206125635.952114-1-abel.vesa@linaro.org> References: <20221206125635.952114-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 000000000000..15176b0457d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h + +properties: + compatible: + const: qcom,sm8550-tcsr + + clocks: + items: + - description: Board XO source + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bindings/clock/qcom,sm8550-tcsr.h new file mode 100644 index 000000000000..091cb76f953a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif -- 2.34.1