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Message-ID: <7fcb4e87-7314-67c9-3217-48687f1ec86b@marcan.st>
Date:   Wed, 7 Dec 2022 13:29:11 +0900
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To:     Janne Grunau <j@jannau.net>, Sven Peter <sven@svenpeter.dev>,
        Alyssa Rosenzweig <alyssa@rosenzweig.io>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc:     asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20221206-asahi-soc-t8103-cache-v1-0-577c5ca2360f@jannau.net>
From:   Hector Martin <marcan@marcan.st>
Subject: Re: [PATCH] arm64: dts: apple: Add t8103 L1/L2 cache properties and
 nodes
In-Reply-To: <20221206-asahi-soc-t8103-cache-v1-0-577c5ca2360f@jannau.net>
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On 07/12/2022 07.38, Janne Grunau wrote:
> The t8103 CPU nodes are missing the cache hierarchy information. The
> cache hierarchy on Arm can not be detected and needs to be described in
> DT. The OS scheduler can make use of this information for scheduling
> decisions.
> 
> The cache size information is based on various articles about the
> processors. There's also an L3 system level cache (SLC). It's not
> described here because SLCs typically have some MMIO interface which
> would need to be described.
> 
> Based on Rob Herring's patch adding cache properties and nodes for
> t600x.
> 
> Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@kernel.org/
> 
> Signed-off-by: Janne Grunau <j@jannau.net>

Acked-by: Hector Martin <marcan@marcan.st>

Thanks! Applied to asahi-soc/dt.

- Hector