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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i14-20020a1709064fce00b007c0889e324esi5157007ejw.366.2022.12.07.01.52.11; Wed, 07 Dec 2022 01:52:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=if8zULPq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230048AbiLGIpu (ORCPT + 76 others); Wed, 7 Dec 2022 03:45:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229968AbiLGIos (ORCPT ); Wed, 7 Dec 2022 03:44:48 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B25D30F47; Wed, 7 Dec 2022 00:44:22 -0800 (PST) X-UUID: 338950f3c73e43f5b648821d3ae2213b-20221207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=gPTg4YGWNDgyxYDKiYXFFlxwfyVSjNJNtKl3X8i7lgo=; b=if8zULPqth+AAh+oFP/QY2OPBAAFXPIeh+qTiTXm2mLm6D1Ac5sGIbg7j2hkbeGLynE5g/jBdeDXggfnhgv8HybB+kLkMHUIBpjCOVLO1F+OkvJzvQ/0fk38OrQ+uA9CHPgiED0w13uoeY5Y848Ud15nvDc25tIcMtOAc5JBANo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:8cad3367-86fd-4074-b3dc-20e4b5c1bf03,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:b8c6e5d1-652d-43fd-a13a-a5dd3c69a43d,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 338950f3c73e43f5b648821d3ae2213b-20221207 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1039616216; Wed, 07 Dec 2022 16:44:14 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 7 Dec 2022 16:44:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 7 Dec 2022 16:44:13 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: , , , , , Moudy Ho Subject: [PATCH v2 04/12] media: platform: mtk-mdp3: add support second sets of MUTEX Date: Wed, 7 Dec 2022 16:44:04 +0800 Message-ID: <20221207084412.14075-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221207084412.14075-1-moudy.ho@mediatek.com> References: <20221207084412.14075-1-moudy.ho@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org After configuring the second set of MMSYS (VPPSYS1), a corresponding second set of MUTEX (MUTEX2) is required to help handle SOF/EOF Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 64 ++++++++++++------- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 30 +++++++-- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 2 + 3 files changed, 67 insertions(+), 29 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index 3617c99f8e4c..5472d7183a5e 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -43,15 +43,28 @@ static bool is_output_disabled(int id, const struct img_compparam *param, u32 co return (count < num) ? (dis_output || dis_tile) : true; } +static struct mtk_mutex *__get_mutex(const struct mdp_dev *mdp_dev, + const struct mdp_pipe_info *p) +{ + struct mtk_mutex *m; + + if (p->mmsys_id) + m = mdp_dev->mdp_mutex2[p->mutex_id]; + else + m = mdp_dev->mdp_mutex[p->mutex_id]; + + return m; +} + static int mdp_path_subfrm_require(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, - s32 *mutex_id, u32 count) + struct mdp_pipe_info *p, u32 count) { const int plat_id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; struct device *dev = &path->mdp_dev->pdev->dev; - struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; + struct mtk_mutex *mutex; int id, index; u32 num_comp = 0; @@ -76,7 +89,8 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, dev_err(dev, "Unknown pipeline and no mutex is assigned"); return -EINVAL; } - *mutex_id = data->pipe_info[index].mutex_id; + memcpy(p, &data->pipe_info[index], sizeof(struct mdp_pipe_info)); + mutex = __get_mutex(path->mdp_dev, p); /* Set mutex mod */ for (index = 0; index < num_comp; index++) { @@ -84,29 +98,28 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, if (is_output_disabled(plat_id, ctx->param, count)) continue; id = ctx->comp->public_id; - mtk_mutex_write_mod(mutex[*mutex_id], - data->mdp_mutex_table_idx[id], false); + mtk_mutex_write_mod(mutex, data->mdp_mutex_table_idx[id], false); + } - mtk_mutex_write_sof(mutex[*mutex_id], - MUTEX_SOF_IDX_SINGLE_MODE); + mtk_mutex_write_sof(mutex, MUTEX_SOF_IDX_SINGLE_MODE); return 0; } static int mdp_path_subfrm_run(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, - s32 *mutex_id, u32 count) + struct mdp_pipe_info *p, u32 count) { const int id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; struct device *dev = &path->mdp_dev->pdev->dev; - struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; + struct mtk_mutex *mutex; int index; u32 num_comp = 0; s32 event; - if (-1 == *mutex_id) { + if (-1 == p->mutex_id) { dev_err(dev, "Incorrect mutex id"); return -EINVAL; } @@ -126,7 +139,8 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, } /* Enable the mutex */ - mtk_mutex_enable_by_cmdq(mutex[*mutex_id], (void *)&cmd->pkt); + mutex = __get_mutex(path->mdp_dev, p); + mtk_mutex_enable_by_cmdq(mutex, (void *)&cmd->pkt); /* Wait SOF events and clear mutex modules (optional) */ for (index = 0; index < num_comp; index++) { @@ -173,7 +187,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, const struct img_mmsys_ctrl *ctrl = NULL; const struct img_mux *set; struct mdp_comp_ctx *ctx; - s32 mutex_id; + struct mdp_pipe_info pipe; int index, ret; u32 num_comp = 0; @@ -184,7 +198,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]); /* Acquire components */ - ret = mdp_path_subfrm_require(path, cmd, &mutex_id, count); + ret = mdp_path_subfrm_require(path, cmd, &pipe, count); if (ret) return ret; /* Enable mux settings */ @@ -203,7 +217,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, return ret; } /* Run components */ - ret = mdp_path_subfrm_run(path, cmd, &mutex_id, count); + ret = mdp_path_subfrm_run(path, cmd, &pipe, count); if (ret) return ret; /* Wait components done */ @@ -327,13 +341,13 @@ static void mdp_auto_release_work(struct work_struct *work) { struct mdp_cmdq_cmd *cmd; struct mdp_dev *mdp; - int id; + struct mtk_mutex *mutex; cmd = container_of(work, struct mdp_cmdq_cmd, auto_release_work); mdp = cmd->mdp; - id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - mtk_mutex_unprepare(mdp->mdp_mutex[id]); + mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]); + mtk_mutex_unprepare(mutex); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -353,7 +367,6 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) struct cmdq_cb_data *data; struct mdp_dev *mdp; struct device *dev; - int id; if (!mssg) { pr_info("%s:no callback data\n", __func__); @@ -378,9 +391,11 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) INIT_WORK(&cmd->auto_release_work, mdp_auto_release_work); if (!queue_work(mdp->clock_wq, &cmd->auto_release_work)) { + struct mtk_mutex *mutex; + dev_err(dev, "%s:queue_work fail!\n", __func__); - id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - mtk_mutex_unprepare(mdp->mdp_mutex[id]); + mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]); + mtk_mutex_unprepare(mutex); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -401,6 +416,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) struct mdp_cmdq_cmd *cmd = NULL; struct mdp_comp *comps = NULL; struct device *dev = &mdp->pdev->dev; + struct mtk_mutex *mutex = NULL; const int id = mdp->mdp_data->mdp_plat_id; int i, ret; u32 num_comp = 0; @@ -437,8 +453,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) goto err_free_comps; } - i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - ret = mtk_mutex_prepare(mdp->mdp_mutex[i]); + mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]); + ret = mtk_mutex_prepare(mutex); if (ret) { dev_err(dev, "Fail to enable mutex clk\n"); goto err_free_path; @@ -503,8 +519,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); err_free_path: - i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - mtk_mutex_unprepare(mdp->mdp_mutex[i]); + if (mutex) + mtk_mutex_unprepare(mutex); kfree(path); err_free_comps: kfree(comps); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 927d3d65751a..56c42bd3f16b 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -161,8 +161,10 @@ void mdp_video_device_release(struct video_device *vdev) vb2_dma_contig_clear_max_seg_size(&mdp->pdev->dev); mdp_comp_destroy(mdp); - for (i = 0; i < MDP_PIPE_MAX; i++) + for (i = 0; i < MDP_PIPE_MAX; i++) { mtk_mutex_put(mdp->mdp_mutex[i]); + mtk_mutex_put(mdp->mdp_mutex2[i]); + } mdp_vpu_shared_mem_free(&mdp->vpu); v4l2_m2m_release(mdp->m2m_dev); @@ -205,12 +207,28 @@ static int mdp_probe(struct platform_device *pdev) ret = -ENODEV; goto err_destroy_device; } + mm2_pdev = __get_pdev_by_id(pdev, mm_pdev, MDP_INFRA_MUTEX2); + /* MUTEX2 must works with MMSYS2 */ + if ((IS_ERR(mm2_pdev)) || + (mm2_pdev && IS_ERR_OR_NULL(mdp->mdp_mmsys2))) { + ret = -ENODEV; + goto err_destroy_device; + } for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { + struct platform_device *p; + struct mtk_mutex **m; + u32 id; + mutex_id = mdp->mdp_data->pipe_info[i].mutex_id; - if (mdp->mdp_mutex[mutex_id]) + id = mdp->mdp_data->pipe_info[i].mmsys_id; + p = (id && mm2_pdev) ? mm2_pdev : mm_pdev; + m = (id && mm2_pdev) ? + mdp->mdp_mutex2 : mdp->mdp_mutex; + + if (m[mutex_id]) continue; - mdp->mdp_mutex[mutex_id] = mtk_mutex_get(&mm_pdev->dev); - if (!mdp->mdp_mutex[mutex_id]) { + m[mutex_id] = mtk_mutex_get(&p->dev); + if (!m[mutex_id]) { ret = -ENODEV; goto err_free_mutex; } @@ -291,8 +309,10 @@ static int mdp_probe(struct platform_device *pdev) err_deinit_comp: mdp_comp_destroy(mdp); err_free_mutex: - for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { mtk_mutex_put(mdp->mdp_mutex[i]); + mtk_mutex_put(mdp->mdp_mutex2[i]); + } err_destroy_device: kfree(mdp); err_return: diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 50c0bc6c358f..3ffad6be95ad 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -22,6 +22,7 @@ enum mdp_infra_id { MDP_INFRA_MMSYS, MDP_INFRA_MMSYS2, MDP_INFRA_MUTEX, + MDP_INFRA_MUTEX2, MDP_INFRA_SCP, MDP_INFRA_MAX }; @@ -71,6 +72,7 @@ struct mdp_dev { struct device *mdp_mmsys; struct device *mdp_mmsys2; struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX]; + struct mtk_mutex *mdp_mutex2[MDP_PIPE_MAX]; struct mdp_comp *comp[MDP_MAX_COMP_COUNT]; const struct mtk_mdp_driver_data *mdp_data; -- 2.18.0