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Date:   Wed, 7 Dec 2022 17:40:29 +0100
From:   Jonathan =?utf-8?Q?Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
To:     Andrew Lunn <andrew@lunn.ch>
Cc:     Jonathan =?utf-8?Q?Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>,
        linux-arm-kernel@lists.infradead.org,
        Robert Jarzmik <robert.jarzmik@free.fr>,
        Haojian Zhuang <haojian.zhuang@gmail.com>,
        Daniel Mack <daniel@zonque.org>, linux-kernel@vger.kernel.org
Subject: Re: PXA25x: GPIO driver fails probe due to resource conflict with
 pinctrl driver
Message-ID: <Y5DB/aUpFrS68DMd@probook>
References: <Y5B4QeNMNboJ42n4@probook>
 <Y5CxBzy47Gjn/V5a@lunn.ch>
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On Wed, Dec 07, 2022 at 04:28:07PM +0100, Andrew Lunn wrote:
> On Wed, Dec 07, 2022 at 12:25:53PM +0100, Jonathan Neusch=C3=A4fer wrote:
> > Hello,
> >=20
> > I am currently trying to bring up Linux 6.1-rcX on a PXA255 board, usin=
g a
> > devicetree. One problem I encountered is that the PXA GPIO driver fails=
 to
> > probe because it uses the same MMIO register range as the pinctrl drive=
r:
> >=20
> > [    0.666169] pxa25x-pinctrl 40e00054.pinctrl: initialized pxa2xx pinc=
trl driver
> > [    0.694407] pxa-gpio 40e00000.gpio: can't request region for resourc=
e [mem 0x40e00000-0x40e0ffff]
> > [    0.695050] pxa-gpio: probe of 40e00000.gpio failed with error -16
> >=20
> > Before I try to fix this myself: Is GPIO on PXA25x currently expected to
> > work and when has it last been seen working?
> >=20
> > What would be a good way to fix this?
>=20
> How are the registers arranged? Is 0x40e00000-0x40e0ffff simply too
> large, and making it smaller would fix the issue? Or are the registers
> interleaved? It is possible to request a region in a non-exclusive
> manor. Or is it more than interleaving, individual registers need to
> be shared between the two drivers? If so, you have the locking issues
> you mentioned.
>=20
>     Andrew

(I wrote this before I saw the other reply, so there are probably
 duplicate information)

They overlap. pxa25x.dtsi declares:

	pinctrl: pinctrl@40e00000 {
		reg =3D <0x40e00054 0x20>,  // base_af[0]
		      <0x40e0000c 0xc>,   // base_dir[0]
		      <0x40e0010c 4>,     // base_dir[3]
		      <0x40f00020 0x10>;  // base_sleep[0]
		compatible =3D "marvell,pxa25x-pinctrl";
	};

(comments mine, based on pinctrl-pxxa25x.c)


The GPIO driver mentions these registers (for PXA25x):

	          GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
	BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
	BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
	BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050

So, there are overlaps in GPDR (0x0c-0x14, GPIO pin direction register).

The register at 0x10c seems bogus for PXA25x: gpio-pxa.c mentions it as
part of bank 3, which only exists in PXA27x or later.


Jonathan

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