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Message-ID: <f277a3cf2e0c51d47c6af0a53547792d727a5a79.camel@linux.intel.com>
Subject: Re: [PATCH V8 0/4] PCI: vmd: Enable PCIe ASPM and LTR on select
 hardware
From:   "David E. Box" <david.e.box@linux.intel.com>
Reply-To: david.e.box@linux.intel.com
To:     Luke Jones <luke@ljones.dev>, nirmal.patel@linux.intel.com,
        jonathan.derrick@linux.dev, lorenzo.pieralisi@arm.com,
        hch@infradead.org, kw@linux.com, robh@kernel.org,
        bhelgaas@google.com, michael.a.bottini@intel.com,
        rafael@kernel.org, me@adhityamohan.in
Cc:     linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Date:   Wed, 07 Dec 2022 18:40:23 -0800
In-Reply-To: <8b8c7ae512291532ea227b8a1c3f87c460e11e2f.camel@ljones.dev>
References: <20221103021822.308586-1-david.e.box@linux.intel.com>
         <8b8c7ae512291532ea227b8a1c3f87c460e11e2f.camel@ljones.dev>
Organization: David E. Box
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On Wed, 2022-12-07 at 22:05 +1300, Luke Jones wrote:
> On Wed, 2022-11-02 at 19:18 -0700, David E. Box wrote:
> > This series adds a work around for enabling PCIe ASPM and for setting
> > PCIe
> > LTR values on VMD reserved root ports on select platforms. While
> > configuration of these capabilities is usually done by BIOS, on these
> > platforms these capabilities will not be configured because the ports
> > are
> > not visible to BIOS. This was part of an initial design that expected
> > the
> > driver to completely handle the ports, including power management.
> > However
> > on Linux those ports are still managed by the PCIe core, which has
> > the
> > expectation that they adhere to device standards including BIOS
> > configuration, leading to this problem.
> >=20
> > The target platforms are Tiger Lake, Alder Lake, and Raptor Lake
> > though the
> > latter has already implemented support for configuring the LTR
> > values.
> > Meteor Lake is expected add BIOS ASPM support, eliminating the future
> > need
> > for this work around.
> >=20
> > Note, the driver programs the LTRs because BIOS would also normally
> > do this
> > for devices that do not set them by default. Without this, SoC power
> > management would be blocked on those platform. This SoC specific
> > value is
> > the maximum latency required to allow the SoC to enter the deepest
> > power
> > state.
> >=20
> > This patch addresses the following open bugzillas on VMD enabled
> > laptops
> > that cannot enter low power states.
> >=20
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D212355
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D215063
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D213717
> >=20
> > David E. Box (3):
> > =C2=A0 PCI: vmd: Use PCI_VDEVICE in device list
> > =C2=A0 PCI: vmd: Create feature grouping for client products
> > =C2=A0 PCI: vmd: Add quirk to configure PCIe ASPM and LTR
> >=20
> > Michael Bottini (1):
> > =C2=A0 PCI/ASPM: Add pci_enable_link_state()
> >=20
> > =C2=A0drivers/pci/controller/vmd.c | 96 ++++++++++++++++++++++++++-----=
---
> > --
> > =C2=A0drivers/pci/pcie/aspm.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 54 ++++++=
++++++++++++++
> > =C2=A0include/linux/pci.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 |=C2=A0 7 +++
> > =C2=A03 files changed, 131 insertions(+), 26 deletions(-)
> >=20
> >=20
> > base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740
>=20
> I'd like to confirm that this patch series solves the VMD power issues
> present on the ASUS ROG M16 (GU603) laptop range (PCI dev ID =3D 467f).
>=20
> The difference is quite drastic.
>=20

Thanks for testing this Luke.

David