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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p3-20020aa79e83000000b005774f410e52si5808088pfq.303.2022.12.07.19.16.46; Wed, 07 Dec 2022 19:16:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229838AbiLHCqL (ORCPT + 75 others); Wed, 7 Dec 2022 21:46:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229760AbiLHCqJ (ORCPT ); Wed, 7 Dec 2022 21:46:09 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9BB0F880F4; Wed, 7 Dec 2022 18:46:07 -0800 (PST) Received: from loongson.cn (unknown [10.20.42.77]) by gateway (Coremail) with SMTP id _____8Cx7+vuT5FjEAMEAA--.9526S3; Thu, 08 Dec 2022 10:46:06 +0800 (CST) Received: from [10.20.42.77] (unknown [10.20.42.77]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxFlfsT5FjMqInAA--.13593S3; Thu, 08 Dec 2022 10:46:05 +0800 (CST) Subject: Re: [PATCH v2 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller To: Rob Herring Cc: Thomas Gleixner , Marc Zyngier , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jianmin Lv , Yinbo Zhu , wanghongliang , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221114113824.1880-1-liupeibao@loongson.cn> <20221114113824.1880-3-liupeibao@loongson.cn> <20221208020954.GA3368836-robh@kernel.org> From: Liu Peibao Message-ID: <62a8ab9a-6b02-a919-c026-d48f7e11264e@loongson.cn> Date: Thu, 8 Dec 2022 10:46:04 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20221208020954.GA3368836-robh@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-CM-TRANSID: AQAAf8BxFlfsT5FjMqInAA--.13593S3 X-CM-SenderInfo: xolx1vpled0qxorr0wxvrqhubq/1tbiAQAOCmOQgmgMegAAsq X-Coremail-Antispam: 1Uk129KBjvJXoW7Zw47ZFWUZF1xZr48Zr18Krg_yoW8AFWxpF y7CFsxWF40qF13Gws2qa4jkrnxZrn3CFn2gan3tw1xKr9Iga47XFW29F95uFW8GrWxXr42 vw1Fga10ga9rJFJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bI8YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCYjI0SjxkI62AI1cAE67vIY487Mx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_ Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8 JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU7_MaUUUUU X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_SBL_CSS,SPF_HELO_PASS,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/8/22 10:09 AM, Rob Herring wrote: > On Mon, Nov 14, 2022 at 07:38:24PM +0800, Liu Peibao wrote: >> Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how >> the 14 IRQs are wired to the platform's internal interrupt controller by >> devicetree. >> >> Signed-off-by: Liu Peibao >> --- >> .../loongarch,cpu-interrupt-controller.yaml | 34 +++++++++++++++++++ >> 1 file changed, 34 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml >> new file mode 100644 >> index 000000000000..2a1cf885c99d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml >> @@ -0,0 +1,34 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: LoongArch CPU Interrupt Controller >> + >> +maintainers: >> + - Liu Peibao >> + >> +properties: >> + compatible: >> + const: loongarch,cpu-interrupt-controller > > This doesn't match what the kernel is using. It has loongson rather than > loongarch. Please send an incremental fix. (Don't forget the example) > > Rob > I will send an incremental fix. It is much embarrassed for my careless. Thanks! BR, Peibao