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Thu, 08 Dec 2022 14:45:55 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2B8Ejsx7021215 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Dec 2022 14:45:54 GMT Received: from [10.216.54.36] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 8 Dec 2022 06:45:46 -0800 Message-ID: <3cd97020-d55a-7808-49f5-5fe3af84dc58@quicinc.com> Date: Thu, 8 Dec 2022 20:15:43 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH v7 0/6] clk/qcom: Support gdsc collapse polling using 'reset' interface Content-Language: en-US To: Ulf Hansson , Bjorn Andersson CC: freedreno , , , Rob Clark , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel , Douglas Anderson , , Abhinav Kumar , Andy Gross , Daniel Vetter , David Airlie , "Konrad Dybcio" , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Sean Paul , Stephen Boyd , , , References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> <20221201225705.46r2m35ketvzipox@builder.lan> <20221207165457.kwdwwiycbwjpogxl@builder.lan> From: Akhil P Oommen In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oSW0SBdBxL6fUr4qAcmvSHnY4Tqwmf6y X-Proofpoint-ORIG-GUID: oSW0SBdBxL6fUr4qAcmvSHnY4Tqwmf6y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-08_08,2022-12-08_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 spamscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212080121 X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/8/2022 7:10 PM, Ulf Hansson wrote: > On Wed, 7 Dec 2022 at 17:55, Bjorn Andersson wrote: >> On Wed, Dec 07, 2022 at 05:00:51PM +0100, Ulf Hansson wrote: >>> On Thu, 1 Dec 2022 at 23:57, Bjorn Andersson wrote: >>>> On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote: >>>> @Ulf, Akhil has a power-domain for a piece of hardware which may be >>>> voted active by multiple different subsystems (co-processors/execution >>>> contexts) in the system. >>>> >>>> As such, during the powering down sequence we don't wait for the >>>> power-domain to turn off. But in the event of an error, the recovery >>>> mechanism relies on waiting for the hardware to settle in a powered off >>>> state. >>>> >>>> The proposal here is to use the reset framework to wait for this state >>>> to be reached, before continuing with the recovery mechanism in the >>>> client driver. >>> I tried to review the series (see my other replies), but I am not sure >>> I fully understand the consumer part. >>> >>> More exactly, when and who is going to pull the reset and at what point? >>> >>>> Given our other discussions on quirky behavior, do you have any >>>> input/suggestions on this? >>>> >>>>> Some clients like adreno gpu driver would like to ensure that its gdsc >>>>> is collapsed at hardware during a gpu reset sequence. This is because it >>>>> has a votable gdsc which could be ON due to a vote from another subsystem >>>>> like tz, hyp etc or due to an internal hardware signal. To allow >>>>> this, gpucc driver can expose an interface to the client driver using >>>>> reset framework. Using this the client driver can trigger a polling within >>>>> the gdsc driver. >>>> @Akhil, this description is fairly generic. As we've reached the state >>>> where the hardware has settled and we return to the client, what >>>> prevents it from being powered up again? >>>> >>>> Or is it simply a question of it hitting the powered-off state, not >>>> necessarily staying there? >>> Okay, so it's indeed the GPU driver that is going to assert/de-assert >>> the reset at some point. Right? >>> >>> That seems like a reasonable approach to me, even if it's a bit >>> unclear under what conditions that could happen. >>> >> Generally the disable-path of the power-domain does not check that the >> power-domain is actually turned off, because the status might indicate >> that the hardware is voting for the power-domain to be on. > Is there a good reason why the HW needs to vote too, when the GPU > driver is already in control? > > Or perhaps that depends on the running use case? This power domain can be voted to be ON from other subsystems outside of linux kernel like secure os, hypervisor etc through separate vote registers. So it is not completely under the control of linux clk driver. Linux clk driver can only vote it to be kept ON, check current status etc, but cannot force it to be OFF. I believe this is why it is a votable gdsc in linux-clk driver. Just a general clarification. GPU has mainly 2 power domains: (1) CX which is shared by GPU and its SMMU, (2) GX which is GPU specific and managed mostly by a power management core within GPU. This patch series is to allow gpu driver to ensure that CX gdsc has collapsed which in turn will reset GPU's internal state. > >> As part of the recovery of the GPU after some fatal fault, the GPU >> driver does something which will cause the hardware votes for the >> power-domain to be let go, and then the driver does pm_runtime_put(). > Okay. That "something", sounds like a device specific setting for the > corresponding gdsc, right? > > So somehow the GPU driver needs to manage that setting, right? Clarified about this above. > >> But in this case the GPU driver wants to ensure that the power-domain is >> actually powered down, before it does pm_runtime_get() again. To ensure >> that the hardware lost its state... > I see. > >> The proposal here is to use a reset to reach into the power-domain >> provider and wait for the hardware to be turned off, before the GPU >> driver attempts turning the power-domain on again. >> >> >> In other words, there is no reset. This is a hack to make a normally >> asynchronous pd.power_off() to be synchronous in this particular case. Not really. Because other non-linux subsystems are involved here for CX gdsc, we need a way to poll the gdsc register to ensure that it has indeed collapsed before gpu driver continue with re-initialization of gpu. It is either this approach using 'reset' framework or plumbing a new path from gpu driver to gpucc-gdsc driver to poll the collapse status. I went with the 'reset' approach as per the consensus here: https://patchwork.freedesktop.org/patch/493143/ -Akhil. > Alright, assuming I understood your clarifications above correctly > (thanks!), I think I have got a much better picture now. > > Rather than abusing the reset interface, I think we should manage this > through the genpd's power on/off notifiers (GENPD_NOTIFY_OFF). The GPU > driver should register its corresponding device for them > (dev_pm_genpd_add_notifier()). > > The trick however, is to make the behaviour of the power-domain for > the gdsc (the genpd->power_off() callback) conditional on whether the > HW is configured to vote or not. If the HW can vote, it should not > poll for the state - and vice versa when the HW can't vote. > > Would this work? > > Kind regards > Uffe