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References: <20221118104300.85016-1-conor@kernel.org>
Subject: Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup
Message-Id: <167054390671.12029.6021322479982022289.b4-ty@rivosinc.com>
Date:   Thu, 08 Dec 2022 15:58:26 -0800
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Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        linux-kernel@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>,
        Conor Dooley <conor.dooley@microchip.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org
From:   Palmer Dabbelt <palmer@rivosinc.com>
To:     Marc Zyngier <maz@kernel.org>, Anup Patel <anup@brainfault.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Conor Dooley <conor@kernel.org>
Precedence: bulk

On Fri, 18 Nov 2022 10:42:58 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Applied, thanks!

[1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
      https://git.kernel.org/palmer/c/fdb1742aff43
[2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
      https://git.kernel.org/palmer/c/d8fb13070c3c
[3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
      https://git.kernel.org/palmer/c/bf3d7b1d8499

Best regards,
-- 
Palmer Dabbelt <palmer@rivosinc.com>