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Subject: Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup
From:   patchwork-bot+linux-riscv@kernel.org
Message-Id: <167054941875.3046.10675797620524560319.git-patchwork-notify@kernel.org>
Date:   Fri, 09 Dec 2022 01:30:18 +0000
References: <20221118104300.85016-1-conor@kernel.org>
In-Reply-To: <20221118104300.85016-1-conor@kernel.org>
To:     Conor Dooley <conor@kernel.org>
Cc:     linux-riscv@lists.infradead.org, maz@kernel.org,
        palmer@dabbelt.com, anup@brainfault.org, tglx@linutronix.de,
        paul.walmsley@sifive.com, aou@eecs.berkeley.edu,
        linux-kernel@vger.kernel.org, conor.dooley@microchip.com
Precedence: bulk

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Fri, 18 Nov 2022 10:42:58 +0000 you wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Here is the summary with links:
  - [v2,1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
    https://git.kernel.org/riscv/c/fdb1742aff43
  - [v2,2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
    https://git.kernel.org/riscv/c/d8fb13070c3c
  - [v2,3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
    https://git.kernel.org/riscv/c/bf3d7b1d8499

You are awesome, thank you!
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