Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp2915982rwb; Fri, 9 Dec 2022 07:49:36 -0800 (PST) X-Google-Smtp-Source: AA0mqf7wi+RYibhMbp0VShNIYmPVizon3IZR8JGoPmDlmshydWsqSuR3ZbtqlX/4y9MXguibPRvy X-Received: by 2002:a17:907:a078:b0:7c0:f213:4485 with SMTP id ia24-20020a170907a07800b007c0f2134485mr5631975ejc.73.1670600975931; Fri, 09 Dec 2022 07:49:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670600975; cv=none; d=google.com; s=arc-20160816; b=Y3WV9qbtOzrKEh3ezbJQhxkz2g1rRlsVUK8EjMDUnwEsNHhPuSDjTCcLS5FROfiUJR HoxFt0sRyH3S0wCQZU8u6nxiFA6P3T1kAiRdyBh6JoT7k33fFLpleheDUq5XyRCgV1GQ 72j/VkpqbvJ+Xaj2qTyoF7Mrnoxyh442LWD68TdAzCVMg6l++W35zKwtyxW2CYxIxhvL lvoZkCD0GF4OsysOrkuh0TZhSp8GzDzH4DaC0wg9hc7XVMNm/q9G9aUg79CDY/W9ljWz Gyyd5nauP35MynUu8AH17R2CI7Y/RqUeRl3o2EIoikQGvnN9EKZsvFSb8oHV4ofpm1ZB 4FLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:feedback-id:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from; bh=FchcXR5XwSExPrMURnDheySGbr2xAmdIFE1XLe78mxc=; b=hMWjpDx9lc7EAdvUPjTcY738cAxOGB+cMBGHYoWRMXTk/Vw5GU4GDxErp/DZ+OPbIk 0W261AaSXUWZneUaTXLFrZlbuOIlp/pxkCdUM3BBL8kYYfDeMBnm40xae3ig1ggbWkp9 dXhd9EFDj8qTlm5JSu+tlAxuBaPGfQCh3jt7iFkU+4iPEW75DSockqCkge+6Y9Y1ZqE0 AEtL3HuEKRIjQCk/yWioTvlrlAbLSdpvPvnyFLPVVUr5jPuOwKqF0aKsLh772XrFl0v/ bYI00DZg4KNmf3FmuIWDg1JTrCjUnJKDWb5CdKmacVtHl/cLl70epuNy/wePoWrQ+824 gfcw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d33-20020a056402402100b004677a9c4b39si1670467eda.91.2022.12.09.07.49.17; Fri, 09 Dec 2022 07:49:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230165AbiLIPF0 (ORCPT + 76 others); Fri, 9 Dec 2022 10:05:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230019AbiLIPFO (ORCPT ); Fri, 9 Dec 2022 10:05:14 -0500 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.155.67.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D591E2189C; Fri, 9 Dec 2022 07:05:12 -0800 (PST) X-QQ-mid: bizesmtp89t1670598279tf8ekbj4 Received: from ubuntu.. ( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 09 Dec 2022 23:04:37 +0800 (CST) X-QQ-SSF: 01200000002000B0C000B00A0000000 X-QQ-FEAT: 7bD38UErqBMse/wQvkTTMEyob1uRl85oGpxpBEZmiEMslPZLCL+kkKP6NtbX2 gPc0PSkUeyw56O8ET95uXwx6vMo+BhrnioINwoXo4H2tTnglrQ/7WRNrtlQxK7ZQxSzw4ba ZeYLrpHEC9pG4k7/gbKQgezfWTytqnhFV+jA16UgOb0XV+eGbyAAhyEZQ7gB/3fFm0ivwFx bdP+CFTqDOLadz2kycFslFhdoxQFI4FDYuWQVzMVw3ReGwgKnFOt8f3+eihWRjuFqXfIje2 KdVb9RsMmhoL4ikneZlRSDmfernerWgzDol1vR6cutPf4eSN8cTqRMCFNRjhWwlE0OvFo4z hbLJM6xeg60PoRG+FB96PPSALEiAg== X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Albert Ou , Catalin Marinas , Greg Kroah-Hartman , Jiri Slaby , Palmer Dabbelt , Paul Walmsley , Russell King , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Date: Fri, 9 Dec 2022 23:04:34 +0800 Message-Id: <20221209150437.795918-1-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RISC-V semihosting spec [1] is built on top of the existing Arm one; we can add RISC-V earlycon semihost driver easily. This series refactors the existing driver a little bit, to move smh_putc() variants in respective arch's semihost.h, then we can implement RISC-V's version in the riscv arch directory. Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] Changes in v3: - add #ifdef in the header to prevent from multiple inclusion - add forward-declare struct uart_port - add a Link tag in the commit message Changes in v2: - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h" - Move the RISC-V implementation to semihost.h Bin Meng (3): serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h riscv: Implement semihost.h for earlycon semihost driver serial: Rename earlycon semihost driver arch/arm/include/asm/semihost.h | 30 +++++++++++++++++++ arch/arm64/include/asm/semihost.h | 24 +++++++++++++++ arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++ drivers/tty/serial/Kconfig | 14 ++++----- drivers/tty/serial/Makefile | 2 +- ...con-arm-semihost.c => earlycon-semihost.c} | 25 +--------------- 6 files changed, 89 insertions(+), 32 deletions(-) create mode 100644 arch/arm/include/asm/semihost.h create mode 100644 arch/arm64/include/asm/semihost.h create mode 100644 arch/riscv/include/asm/semihost.h rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%) -- 2.34.1