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From:   Zhang Chen <chen.zhang@intel.com>
To:     x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc:     Zhang Chen <chen.zhang@intel.com>, Chao Gao <chao.gao@intel.com>,
        Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <seanjc@google.com>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
        Thomas Gleixner <tglx@linutronix.de>
Subject: [RFC PATCH 9/9] x86/kvm/vmx: Initialize SPEC_CTRL MASK for BHI
Date:   Sun, 11 Dec 2022 00:00:46 +0800
Message-Id: <20221210160046.2608762-10-chen.zhang@intel.com>
In-Reply-To: <20221210160046.2608762-1-chen.zhang@intel.com>
References: <20221210160046.2608762-1-chen.zhang@intel.com>
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VMMs can address mitigations issues in migration pool by applying
the needed controls whenever the guest is operating on a newer
processor. If a guest is using the BHB-clearing sequence
on transitions into CPL0 to mitigate BHI, the VMM can use the
“virtual IA32_SPEC_CTRL” VM-execution control to set BHI_DIS_S
on newer hardware which does not enumerate BHI_NO.

Signed-off-by: Zhang Chen <chen.zhang@intel.com>
---
 arch/x86/kvm/vmx/vmx.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index fb0f3b1639b9..980d1ace9718 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2431,6 +2431,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		else
 			vmx->spec_ctrl_mask &= ~SPEC_CTRL_RRSBA_DIS_S;
 
+		if (data & MITI_CTRL_BHB_CLEAR_SEQ_S_USED &&
+		    kvm_cpu_cap_has(X86_FEATURE_BHI_CTRL) &&
+		    !(arch_msr & ARCH_CAP_BHI_NO))
+			vmx->spec_ctrl_mask |= SPEC_CTRL_BHI_DIS_S;
+		else
+			vmx->spec_ctrl_mask &= ~SPEC_CTRL_BHI_DIS_S;
+
 		if (cpu_has_virt_spec_ctrl()) {
 			vmcs_write64(IA32_SPEC_CTRL_MASK, vmx->spec_ctrl_mask);
 		} else if (vmx->spec_ctrl_mask) {
-- 
2.25.1