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Hallyn" , Shuah Khan , bpf , LSM List , "open list:KERNEL SELFTEST FRAMEWORK" , LKML , Roberto Sassu Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 7, 2022 at 9:25 AM Roberto Sassu wrote: > > From: Roberto Sassu > > BPF LSM needs a reliable source of information to determine if the return > value given by eBPF programs is acceptable or not. At the moment, choosing > either the 64 bit or the 32 bit one does not seem to be an option > (selftests fail). > > If we choose the 64 bit one, the following happens. > > 14: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0) > 15: 74 00 00 00 15 00 00 00 w0 >>= 21 > 16: 54 00 00 00 01 00 00 00 w0 &= 1 > 17: 04 00 00 00 ff ff ff ff w0 += -1 > > This is the last part of test_deny_namespace. After #16, the register > values are: > > smin_value = 0x0, smax_value = 0x1, > s32_min_value = 0x0, s32_max_value = 0x1, > > After #17, they become: > > smin_value = 0x0, smax_value = 0xffffffff, > s32_min_value = 0xffffffff, s32_max_value = 0x0 > > where only the 32 bit values are correct. > > If we choose the 32 bit ones, the following happens. > > 0000000000000000 : > 0: 79 12 00 00 00 00 00 00 r2 = *(u64 *)(r1 + 0) > 1: 79 10 08 00 00 00 00 00 r0 = *(u64 *)(r1 + 8) > 2: 67 00 00 00 3e 00 00 00 r0 <<= 62 > 3: c7 00 00 00 3f 00 00 00 r0 s>>= 63 > > This is part of test_libbpf_get_fd_by_id_opts (no_alu32 version). In this > case, 64 bit register values should be used (for the 32 bit ones, there is > no precise information from the verifier). > > As the examples above suggest that which register values to use depends on > the specific case, mark ALU32 operations in bpf_reg_state structure, so > that BPF LSM can choose the proper ones. I have a hard time understanding what is the problem you're trying to solve and what is the proposed fix. The patch is trying to remember the bitness of the last operation, but what for? The registers are 64-bit. There are 32-bit operations, but they always update the upper 32-bits of the register. reg_bounds_sync() updates 32 and 64 bit bounds regardless whether the previous operation was on 32 or 64 bit. It seems you're trying to hack around something that breaks patch 3 which also looks fishy. Please explain the problem first with a concrete example.