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From:   "Yuan, Perry" <Perry.Yuan@amd.com>
To:     "Huang, Ray" <Ray.Huang@amd.com>
CC:     "rafael.j.wysocki@intel.com" <rafael.j.wysocki@intel.com>,
        "Limonciello, Mario" <Mario.Limonciello@amd.com>,
        "viresh.kumar@linaro.org" <viresh.kumar@linaro.org>,
        "Sharma, Deepak" <Deepak.Sharma@amd.com>,
        "Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
        "Deucher, Alexander" <Alexander.Deucher@amd.com>,
        "Huang, Shimmer" <Shimmer.Huang@amd.com>,
        "Du, Xiaojian" <Xiaojian.Du@amd.com>,
        "Meng, Li (Jassmine)" <Li.Meng@amd.com>,
        "Karny, Wyes" <Wyes.Karny@amd.com>,
        "linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v7 01/13] ACPI: CPPC: Add AMD pstate energy performance
 preference cppc control
Thread-Topic: [PATCH v7 01/13] ACPI: CPPC: Add AMD pstate energy performance
 preference cppc control
Thread-Index: AQHZCvbtROnCBcp0JUOaXLGbvuivq65lMScAgARszACAAGEJcA==
Date:   Mon, 12 Dec 2022 09:17:31 +0000
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References: <20221208111852.386731-1-perry.yuan@amd.com>
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[AMD Official Use Only - General]

Hi Ray.

> -----Original Message-----
> From: Huang, Ray <Ray.Huang@amd.com>
> Sent: Monday, December 12, 2022 11:29 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>
> Cc: rafael.j.wysocki@intel.com; Limonciello, Mario
> <Mario.Limonciello@amd.com>; viresh.kumar@linaro.org; Sharma, Deepak
> <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; Karny, Wyes <Wyes.Karny@amd.com>;
> linux-pm@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v7 01/13] ACPI: CPPC: Add AMD pstate energy
> performance preference cppc control
>=20
> On Fri, Dec 09, 2022 at 03:55:28PM +0800, Huang Rui wrote:
> > On Thu, Dec 08, 2022 at 07:18:40PM +0800, Yuan, Perry wrote:
> > > From: Perry Yuan <Perry.Yuan@amd.com>
> > >
> > > Add support for setting and querying EPP preferences to the generic
> > > CPPC driver.  This enables downstream drivers such as amd-pstate to
> > > discover and use these values
> > >
> > > Downstream drivers that want to use the new symbols
> > > cppc_get_epp_caps and cppc_set_epp_perf for querying and setting EPP
> > > preferences will need to call cppc_set_auto_epp to enable the EPP
> function first.
> > >
> > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> >
> > Acked-by: Huang Rui <ray.huang@amd.com>
> >
> > > ---
> > >  drivers/acpi/cppc_acpi.c | 114
> > > +++++++++++++++++++++++++++++++++++++--
> > >  include/acpi/cppc_acpi.h |  12 +++++
> > >  2 files changed, 121 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > > index 093675b1a1ff..37fa75f25f62 100644
> > > --- a/drivers/acpi/cppc_acpi.c
> > > +++ b/drivers/acpi/cppc_acpi.c
> > > @@ -1093,6 +1093,9 @@ static int cppc_get_perf(int cpunum, enum
> > > cppc_regs reg_idx, u64 *perf)  {
> > >  	struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum);
> > >  	struct cpc_register_resource *reg;
> > > +	int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum);
> > > +	struct cppc_pcc_data *pcc_ss_data =3D NULL;
> > > +	int ret =3D -EINVAL;
> > >
> > >  	if (!cpc_desc) {
> > >  		pr_debug("No CPC descriptor for CPU:%d\n", cpunum); @@
> -1102,10
> > > +1105,6 @@ static int cppc_get_perf(int cpunum, enum cppc_regs
> reg_idx, u64 *perf)
> > >  	reg =3D &cpc_desc->cpc_regs[reg_idx];
> > >
> > >  	if (CPC_IN_PCC(reg)) {
> > > -		int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum);
> > > -		struct cppc_pcc_data *pcc_ss_data =3D NULL;
> > > -		int ret =3D 0;
> > > -
> > >  		if (pcc_ss_id < 0)
> > >  			return -EIO;
> > >
> > > @@ -1125,7 +1124,7 @@ static int cppc_get_perf(int cpunum, enum
> > > cppc_regs reg_idx, u64 *perf)
> > >
> > >  	cpc_read(cpunum, reg, perf);
> > >
> > > -	return 0;
> > > +	return ret;
> > >  }
> > >
> > >  /**
> > > @@ -1365,6 +1364,111 @@ int cppc_get_perf_ctrs(int cpunum, struct
> > > cppc_perf_fb_ctrs *perf_fb_ctrs)  }
> > > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> > >
> > > +/**
> > > + * cppc_get_epp_caps - Get the energy preference register value.
> > > + * @cpunum: CPU from which to get epp preference level.
> > > + * @perf_caps: Return address.
> > > + *
> > > + * Return: 0 for success, -EIO otherwise.
> > > + */
> > > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
>=20
> Take a look at the patch again, due to the energy_perf is actually one of=
 the
> members in struct cppc_perf_caps. It's better to modify the existing
> cppc_get_perf_caps() to get the epp value as well.
>=20
> Thanks,
> Ray

Makes sense, I will change it in the V8.

Perry.

>=20
> > > +{
> > > +	struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum);
> > > +	struct cpc_register_resource *energy_perf_reg;
> > > +	u64 energy_perf;
> > > +
> > > +	if (!cpc_desc) {
> > > +		pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
> > > +		return -ENODEV;
> > > +	}
> > > +
> > > +	energy_perf_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF];
> > > +
> > > +	if (!CPC_SUPPORTED(energy_perf_reg))
> > > +		pr_warn_once("energy perf reg update is unsupported!\n");
> > > +
> > > +	if (CPC_IN_PCC(energy_perf_reg)) {
> > > +		int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum);
> > > +		struct cppc_pcc_data *pcc_ss_data =3D NULL;
> > > +		int ret =3D 0;
> > > +
> > > +		if (pcc_ss_id < 0)
> > > +			return -ENODEV;
> > > +
> > > +		pcc_ss_data =3D pcc_data[pcc_ss_id];
> > > +
> > > +		down_write(&pcc_ss_data->pcc_lock);
> > > +
> > > +		if (send_pcc_cmd(pcc_ss_id, CMD_READ) >=3D 0) {
> > > +			cpc_read(cpunum, energy_perf_reg, &energy_perf);
> > > +			perf_caps->energy_perf =3D energy_perf;
> > > +		} else {
> > > +			ret =3D -EIO;
> > > +		}
> > > +
> > > +		up_write(&pcc_ss_data->pcc_lock);
> > > +
> > > +		return ret;
> > > +	}
> > > +
> > > +	return 0;
> > > +}
> > > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> > > +
> > > +/*
> > > + * Set Energy Performance Preference Register value through
> > > + * Performance Controls Interface
> > > + */
> > > +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls,
> > > +bool enable) {
> > > +	int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu);
> > > +	struct cpc_register_resource *epp_set_reg;
> > > +	struct cpc_register_resource *auto_sel_reg;
> > > +	struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu);
> > > +	struct cppc_pcc_data *pcc_ss_data =3D NULL;
> > > +	int ret =3D -EINVAL;
> > > +
> > > +	if (!cpc_desc) {
> > > +		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
> > > +		return -ENODEV;
> > > +	}
> > > +
> > > +	auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > > +	epp_set_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF];
> > > +
> > > +	if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
> > > +		if (pcc_ss_id < 0) {
> > > +			pr_debug("Invalid pcc_ss_id\n");
> > > +			return -ENODEV;
> > > +		}
> > > +
> > > +		if (CPC_SUPPORTED(auto_sel_reg)) {
> > > +			ret =3D cpc_write(cpu, auto_sel_reg, enable);
> > > +			if (ret)
> > > +				return ret;
> > > +		}
> > > +
> > > +		if (CPC_SUPPORTED(epp_set_reg)) {
> > > +			ret =3D cpc_write(cpu, epp_set_reg, perf_ctrls-
> >energy_perf);
> > > +			if (ret)
> > > +				return ret;
> > > +		}
> > > +
> > > +		pcc_ss_data =3D pcc_data[pcc_ss_id];
> > > +
> > > +		down_write(&pcc_ss_data->pcc_lock);
> > > +		/* after writing CPC, transfer the ownership of PCC to
> platform */
> > > +		ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > +		up_write(&pcc_ss_data->pcc_lock);
> > > +	} else {
> > > +		ret =3D -ENOTSUPP;
> > > +		pr_debug("_CPC in PCC is not supported\n");
> > > +	}
> > > +
> > > +	return ret;
> > > +}
> > > +EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
> > > +
> > >  /**
> > >   * cppc_set_enable - Set to enable CPPC on the processor by writing =
the
> > >   * Continuous Performance Control package EnableRegister field.
> > > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> > > index c5614444031f..a45bb876a19c 100644
> > > --- a/include/acpi/cppc_acpi.h
> > > +++ b/include/acpi/cppc_acpi.h
> > > @@ -108,12 +108,14 @@ struct cppc_perf_caps {
> > >  	u32 lowest_nonlinear_perf;
> > >  	u32 lowest_freq;
> > >  	u32 nominal_freq;
> > > +	u32 energy_perf;
> > >  };
> > >
> > >  struct cppc_perf_ctrls {
> > >  	u32 max_perf;
> > >  	u32 min_perf;
> > >  	u32 desired_perf;
> > > +	u32 energy_perf;
> > >  };
> > >
> > >  struct cppc_perf_fb_ctrs {
> > > @@ -149,6 +151,8 @@ extern bool cpc_ffh_supported(void);  extern
> > > bool cpc_supported_by_cpu(void);  extern int cpc_read_ffh(int
> > > cpunum, struct cpc_reg *reg, u64 *val);  extern int
> > > cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
> > > +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps
> > > +*perf_caps); extern int cppc_set_epp_perf(int cpu, struct
> > > +cppc_perf_ctrls *perf_ctrls, bool enable);
> > >  #else /* !CONFIG_ACPI_CPPC_LIB */
> > >  static inline int cppc_get_desired_perf(int cpunum, u64
> > > *desired_perf)  { @@ -202,6 +206,14 @@ static inline int
> > > cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)  {
> > >  	return -ENOTSUPP;
> > >  }
> > > +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls
> > > +*perf_ctrls, bool enable) {
> > > +	return -ENOTSUPP;
> > > +}
> > > +static inline int cppc_get_epp_caps(int cpunum, struct
> > > +cppc_perf_caps *perf_caps) {
> > > +	return -ENOTSUPP;
> > > +}
> > >  #endif /* !CONFIG_ACPI_CPPC_LIB */
> > >
> > >  #endif /* _CPPC_ACPI_H*/
> > > --
> > > 2.34.1
> > >