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Date:   Mon, 12 Dec 2022 13:18:53 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        linux-arm-msm@vger.kernel.org, andersson@kernel.org,
        agross@kernel.org, krzysztof.kozlowski@linaro.org
CC:     marijn.suijten@somainline.org, Rob Clark <robdclark@gmail.com>,
        Abhinav Kumar <quic_abhinavk@quicinc.com>,
        Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] arm64: dts: qcom: sm8150: Add DISPCC node
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On 12 December 2022 12:33:13 GMT+03:00, Konrad Dybcio <konrad=2Edybcio@lin=
aro=2Eorg> wrote:
>Years after the SoC support has been added, it's high time for it to
>get dispcc going=2E Add the node to ensure that=2E
>
>Signed-off-by: Konrad Dybcio <konrad=2Edybcio@linaro=2Eorg>
>---
> arch/arm64/boot/dts/qcom/sm8150=2Edtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/qcom/sm8150=2Edtsi b/arch/arm64/boot/dts=
/qcom/sm8150=2Edtsi
>index a0c57fb798d3=2E=2Eff04397777f4 100644
>--- a/arch/arm64/boot/dts/qcom/sm8150=2Edtsi
>+++ b/arch/arm64/boot/dts/qcom/sm8150=2Edtsi
>@@ -3579,6 +3579,32 @@ camnoc_virt: interconnect@ac00000 {
> 			qcom,bcm-voters =3D <&apps_bcm_voter>;
> 		};
>=20
>+		dispcc: clock-controller@af00000 {
>+			compatible =3D "qcom,sm8150-dispcc";
>+			reg =3D <0 0x0af00000 0 0x10000>;
>+			clocks =3D <&rpmhcc RPMH_CXO_CLK>,
>+				 <0>,
>+				 <0>,
>+				 <0>,
>+				 <0>,
>+				 <0>,
>+				 <0>;
>+			clock-names =3D "bi_tcxo",
>+				      "dsi0_phy_pll_out_byteclk",
>+				      "dsi0_phy_pll_out_dsiclk",
>+				      "dsi1_phy_pll_out_byteclk",
>+				      "dsi1_phy_pll_out_dsiclk",
>+				      "dp_phy_pll_link_clk",
>+				      "dp_phy_pll_vco_div_clk";
>+			#clock-cells =3D <1>;
>+			#reset-cells =3D <1>;
>+			#power-domain-cells =3D <1>;
>+
>+			power-domains =3D <&rpmhpd SM8150_MMCX>;
>+			/* TODO: Maybe rpmhpd_opp_min_svs could work as well? */
>+			required-opps =3D <&rpmhpd_opp_low_svs>;

Is it required for the dispcc, for the DSI or for the dpu? We have stumble=
d upon the similar issue when working on the 8350, see the latest Robert's =
patchset=2E


>+		};
>+
> 		pdc: interrupt-controller@b220000 {
> 			compatible =3D "qcom,sm8150-pdc", "qcom,pdc";
> 			reg =3D <0 0x0b220000 0 0x400>;

--=20
With best wishes
Dmitry