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Message-ID: <2b5d33a1-4f8d-e1db-67ef-7e5c32d1ee83@denx.de>
Date:   Mon, 12 Dec 2022 14:01:10 +0100
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Subject: Re: [PATCH 2/4] ARM: dts: stm32: Fix qspi pinctrl phandle for
 stm32mp15xx-dhcom-som
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To:     patrice.chotard@foss.st.com, robh+dt@kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        alexandre.torgue@foss.st.com
Cc:     mcoquelin.stm32@gmail.com,
        linux-stm32@st-md-mailman.stormreply.com, linux@armlinux.org.uk,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org,
        Alexandre Torgue <alexandre.torgue@st.com>
References: <20221212085142.3944367-1-patrice.chotard@foss.st.com>
 <20221212085142.3944367-3-patrice.chotard@foss.st.com>
From:   Marek Vasut <marex@denx.de>
In-Reply-To: <20221212085142.3944367-3-patrice.chotard@foss.st.com>
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On 12/12/22 09:51, patrice.chotard@foss.st.com wrote:
> From: Patrice Chotard <patrice.chotard@foss.st.com>
> 
> Chip select pinctrl phandle was missing in several stm32mp15x based boards.
> 
> Fixes: ea99a5a02ebc ("ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi)
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Alexandre Torgue <alexandre.torgue@st.com>
> Cc: linux-stm32@st-md-mailman.stormreply.com
> To: linux-arm-kernel@lists.infradead.org
> ---
>   arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
> index 238a611192e7..d3b85a8764d7 100644
> --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
> @@ -428,8 +428,12 @@ &pwr_regulators {
>   
>   &qspi {
>   	pinctrl-names = "default", "sleep";
> -	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
> -	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
> +	pinctrl-0 = <&qspi_clk_pins_a
> +		     &qspi_bk1_pins_a
> +		     &qspi_cs1_pins_a>;
> +	pinctrl-1 = <&qspi_clk_sleep_pins_a
> +		     &qspi_bk1_sleep_pins_a
> +		     &qspi_cs1_sleep_pins_a>;
>   	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
>   	#address-cells = <1>;
>   	#size-cells = <0>;

Splitting the pins makes sense indeed.

Reviewed-by: Marek Vasut <marex@denx.de>