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Message-ID: <1be71e47-fba3-4795-6950-de3229961215@quicinc.com>
Date:   Mon, 12 Dec 2022 23:19:40 +0530
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Subject: Re: [PATCH v7 4/6] clk: qcom: gpucc-sc7280: Add cx collapse reset
 support
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To:     Bjorn Andersson <andersson@kernel.org>
CC:     Ulf Hansson <ulf.hansson@linaro.org>,
        freedreno <freedreno@lists.freedesktop.org>,
        <dri-devel@lists.freedesktop.org>, <linux-arm-msm@vger.kernel.org>,
        Rob Clark <robdclark@gmail.com>,
        Stephen Boyd <swboyd@chromium.org>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Douglas Anderson <dianders@chromium.org>,
        <krzysztof.kozlowski@linaro.org>, Andy Gross <agross@kernel.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com>
 <20221005143618.v7.4.I5e64ff4b77bb9079eb2edeea8a02585c9e76778f@changeid>
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 <76812eb1-ef4a-48b3-7b7a-231adc8c7c36@quicinc.com>
 <20221208210929.capfm7jaltxvgpvq@builder.lan>
From:   Akhil P Oommen <quic_akhilpo@quicinc.com>
In-Reply-To: <20221208210929.capfm7jaltxvgpvq@builder.lan>
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On 12/9/2022 2:39 AM, Bjorn Andersson wrote:
> On Thu, Dec 08, 2022 at 08:54:39PM +0530, Akhil P Oommen wrote:
>> On 12/7/2022 9:16 PM, Ulf Hansson wrote:
>>> On Wed, 5 Oct 2022 at 11:08, Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>>>> Allow a consumer driver to poll for cx gdsc collapse through Reset
>>>> framework.
>>> Would you mind extending this commit message, to allow us to better
>>> understand what part is really the consumer part.
>> Sure. I can do that.
>>> I was expecting the consumer part to be the GPU (adreno) driver, but I
>>> may have failed to understand correctly. It would be nice to see an
>>> example of a typical sequence, where the reset is being
>>> asserted/deasserted, from the consumer point of view. Would you mind
>>> explaining this a bit more?
>> https://elixir.bootlin.com/linux/v6.1-rc8/source/drivers/gpu/drm/msm/adreno/a6xx_gpu.c#L1309
>> You are correct. The consumer is adreno gpu driver. When there is a gpu fault, these sequences are followed:
>> 1. drop pm_runtime_put() for gpu device which will drops its vote on 'cx' genpd. line: 1306
>> 2. At this point, there could be vote from either smmu driver (smmu is under same power domain too) or from other subsystems (tz/hyp).
> Can you confirm that this is happening completely independent of what
> the kernel does?
Yes, it is independent.
>
>> 3. So we call into gdsc driver through reset interface to poll the gdsc register to ensure it collapsed at least once. Line: 1309
> I other words, if we engineered 1. such that it would wait in
> gdsc_disable() until the condition for 3. is reached, that should work
> for you? (Obviously depending on the ability for us to engineer this...)
Yes, it will work.

-Akhil.
>
> Regards,
> Bjorn
>
>> 4. Then we turn ON gpu. line:1314.
>>
>> -Akhil.
>>>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> Kind regards
>>> Uffe
>>>
>>>> ---
>>>>
>>>> (no changes since v3)
>>>>
>>>> Changes in v3:
>>>> - Convert 'struct qcom_reset_ops cx_gdsc_reset' to 'static const' (Krzysztof)
>>>>
>>>> Changes in v2:
>>>> - Minor update to use the updated custom reset ops implementation
>>>>
>>>>  drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++++
>>>>  1 file changed, 10 insertions(+)
>>>>
>>>> diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
>>>> index 9a832f2..fece3f4 100644
>>>> --- a/drivers/clk/qcom/gpucc-sc7280.c
>>>> +++ b/drivers/clk/qcom/gpucc-sc7280.c
>>>> @@ -433,12 +433,22 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = {
>>>>         .fast_io = true,
>>>>  };
>>>>
>>>> +static const struct qcom_reset_ops cx_gdsc_reset = {
>>>> +       .reset = gdsc_wait_for_collapse,
>>>> +};
>>>> +
>>>> +static const struct qcom_reset_map gpucc_sc7280_resets[] = {
>>>> +       [GPU_CX_COLLAPSE] = { .ops = &cx_gdsc_reset, .priv = &cx_gdsc },
>>>> +};
>>>> +
>>>>  static const struct qcom_cc_desc gpu_cc_sc7280_desc = {
>>>>         .config = &gpu_cc_sc7280_regmap_config,
>>>>         .clks = gpu_cc_sc7280_clocks,
>>>>         .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks),
>>>>         .gdscs = gpu_cc_sc7180_gdscs,
>>>>         .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
>>>> +       .resets = gpucc_sc7280_resets,
>>>> +       .num_resets = ARRAY_SIZE(gpucc_sc7280_resets),
>>>>  };
>>>>
>>>>  static const struct of_device_id gpu_cc_sc7280_match_table[] = {
>>>> --
>>>> 2.7.4
>>>>