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[78.150.37.98]) by smtp.gmail.com with ESMTPSA id t123-20020a1c4681000000b003a3170a7af9sm10156808wma.4.2022.12.12.10.07.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:07:48 -0800 (PST) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: jude.onyenegecha@sifive.com, ben.dooks@sifive.com, jeegar.lakhani@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudip Mukherjee Subject: [PATCH v2 08/15] spi: dw: update irq setup to use multiple handler Date: Mon, 12 Dec 2022 18:07:25 +0000 Message-Id: <20221212180732.79167-9-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221212180732.79167-1-sudip.mukherjee@sifive.com> References: <20221212180732.79167-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current mem_ops is not using interrupt based transfer so dw_spi_irq_setup() only has one interrput handler to handle the non mem_ops transfers. We will use interrupt based transfers in enhanced spi and so we need a way to specify which irq handler to use. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index ecab0fbc847c7..f540165245a89 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -260,7 +260,8 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) if (!irq_status) return IRQ_NONE; - if (!master->cur_msg) { + if (!master->cur_msg && dws->transfer_handler == + dw_spi_transfer_handler) { dw_spi_mask_intr(dws, 0xff); return IRQ_HANDLED; } @@ -380,7 +381,8 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, } EXPORT_SYMBOL_NS_GPL(dw_spi_update_config, SPI_DW_CORE); -static void dw_spi_irq_setup(struct dw_spi *dws) +static void dw_spi_irq_setup(struct dw_spi *dws, + irqreturn_t (*t_handler)(struct dw_spi *)) { u16 level; u8 imask; @@ -394,7 +396,7 @@ static void dw_spi_irq_setup(struct dw_spi *dws) dw_writel(dws, DW_SPI_TXFTLR, level); dw_writel(dws, DW_SPI_RXFTLR, level - 1); - dws->transfer_handler = dw_spi_transfer_handler; + dws->transfer_handler = t_handler; imask = DW_SPI_INT_TXEI | DW_SPI_INT_TXOI | DW_SPI_INT_RXUI | DW_SPI_INT_RXOI | DW_SPI_INT_RXFI; @@ -486,7 +488,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, else if (dws->irq == IRQ_NOTCONNECTED) return dw_spi_poll_transfer(dws, transfer); - dw_spi_irq_setup(dws); + dw_spi_irq_setup(dws, dw_spi_transfer_handler); return 1; } -- 2.30.2