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Message-ID: <c4ef3f7f-5b1d-5a11-f869-d1c61dd2c26e@linaro.org>
Date:   Wed, 14 Dec 2022 09:09:06 +0100
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Subject: Re: [PATCH 1/4] arm64: dts: qcom: Introduce a carveout for modem
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To:     Sibi Sankar <quic_sibis@quicinc.com>, andersson@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
        manivannan.sadhasivam@linaro.org
Cc:     agross@kernel.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        konrad.dybcio@somainline.org, amit.pundir@linaro.org,
        regressions@leemhuis.info, sumit.semwal@linaro.org,
        will@kernel.org, catalin.marinas@arm.com, robin.murphy@arm.com
References: <20221213140724.8612-1-quic_sibis@quicinc.com>
 <20221213140724.8612-2-quic_sibis@quicinc.com>
 <7ea03855-4806-f4ca-e0c3-4044e1095d6b@linaro.org>
 <96c1e60d-de12-5e60-4c06-70ea4b9c49f8@quicinc.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <96c1e60d-de12-5e60-4c06-70ea4b9c49f8@quicinc.com>
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On 14/12/2022 07:49, Sibi Sankar wrote:
> Hey Krzysztof,
> 
> Thanks for taking time to review the series.
> 
> On 12/14/22 01:10, Krzysztof Kozlowski wrote:
>> On 13/12/2022 15:07, Sibi Sankar wrote:
>>> Introduce a new carveout for modem metadata. This will serve as a
>>> replacement for the memory region used by MSA to authenticate modem
>>> ELF headers.
>>>
>>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>>   
>>>   	aliases {
>>> @@ -865,7 +870,7 @@ hp_i2c: &i2c9 {
>>>   	clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo";
>>>   
>>>   	iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
>>> -	memory-region = <&mba_mem &mpss_mem>;
>>> +	memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
>>>   
>>>   	/* This gets overridden for SKUs with LTE support. */
>>>   	firmware-name = "qcom/sc7180-trogdor/modem-nolte/mba.mbn",
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
>>> index bf522a64b172..bda0495aa0b5 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
>>> @@ -17,6 +17,11 @@
>>>   			reg = <0x0 0x9c700000 0x0 0x200000>;
>>>   			no-map;
>>>   		};
>>> +
>>> +		mdata_mem: memory@9d100000 {
>>> +			reg = <0x0 0x9d100000 0x0 0x4000>;
>>> +			no-map;
>>> +		};
>>>   	};
>>>   };
>>>   
>>> @@ -32,7 +37,7 @@
>>>   
>>>   	iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
>>>   	interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
>>> -	memory-region = <&mba_mem>, <&mpss_mem>;
>>> +	memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
>>
>> Only two memory regions are allowed by bindings... unless you fix it in
>> further patchset. If so, please re-order to have the bindings first. It
>> helps reviewers not to have such questions. :)
> 
> I felt that Rob's dt_bindings check bot might report an error
> if the dt changes weren't placed before the bindings changes.
> But since you asked for the logical order I guess the bindings
> check are done only after the entire series is applied. I'll
> change the order in the next re-spin.

AFAIR, Rob's bot ignores DTS patches anyway.

Best regards,
Krzysztof