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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j10-20020a62b60a000000b0056bf15d0cbfsi2357371pff.308.2022.12.15.04.19.22; Thu, 15 Dec 2022 04:19:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=crkgtFRP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229588AbiLOMAi (ORCPT + 68 others); Thu, 15 Dec 2022 07:00:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiLOMAd (ORCPT ); Thu, 15 Dec 2022 07:00:33 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98C102CCA8; Thu, 15 Dec 2022 04:00:26 -0800 (PST) X-UUID: 65af131f4ccc49eab05b8b5b2817ebc0-20221215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wEtcKJxSE9mxxuhtX/9piOaTQKW2w7JZNGu4dtoOPgQ=; b=crkgtFRPQ4te7/X2zeYhDY7MKNEdoyAWrRZbfZwg6hI2Ns/XvdIEow2ow9du8tTlQ16UJtR4abICdB6aSiqSYQJM9ilyRuJrUY9/5LYP0Fp4+amGRuMrpboZHEhpoYUa7BIJzztQSzS6P7BlisxvlJAwcku5kuiSoQfbMlkECa8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:dcf50cbd-15ab-4cec-98a4-68feb5e1f5ee,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:30725635-a6a3-44f7-8aad-08fee1939a08,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 65af131f4ccc49eab05b8b5b2817ebc0-20221215 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2031610687; Thu, 15 Dec 2022 20:00:20 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 15 Dec 2022 20:00:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Dec 2022 20:00:18 +0800 From: Allen-KH Cheng To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , Stephen Boyd , Ikjoon Jang CC: , , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH 1/4] dt-bindings: power: Add MT8192 ADSP power domain Date: Thu, 15 Dec 2022 20:00:13 +0800 Message-ID: <20221215120016.26611-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221215120016.26611-1-allen-kh.cheng@mediatek.com> References: <20221215120016.26611-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add power domain ID for the ADSP power partition found on MT8192 SoC. Signed-off-by: Allen-KH Cheng --- include/dt-bindings/power/mt8192-power.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h index 4eaa53d7270a..63e81cd0d06d 100644 --- a/include/dt-bindings/power/mt8192-power.h +++ b/include/dt-bindings/power/mt8192-power.h @@ -28,5 +28,6 @@ #define MT8192_POWER_DOMAIN_CAM_RAWA 18 #define MT8192_POWER_DOMAIN_CAM_RAWB 19 #define MT8192_POWER_DOMAIN_CAM_RAWC 20 +#define MT8192_POWER_DOMAIN_ADSP 21 #endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ -- 2.18.0