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Thread-Topic: [v2] pwm: xilinx: Fix u32 overflow issue in 32-bit width PWM mode. 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: designlinxhs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ0P222MB0107.NAMP222.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 23d6cb3f-520e-4fb6-260e-08dadeb66f36 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Dec 2022 16:07:15.7267 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 21db78a4-85a8-43a2-9030-593b170ddfa9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: qOAink/fv6odIvebhA1EWEX/CwE40amNCwDlI7T2gAMtPvjlq/FDRGULo0vy+9wJiVKy7YaonXlo/6T5V86Mfw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1P222MB0359 X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,T_SPF_PERMERROR autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ken Sloat =0A= =0A= This timer HW supports 8, 16 and 32-bit timer widths. This=0A= driver currently uses a u32 to store the max possible value=0A= of the timer. However, statements perform addition of 2 in=0A= xilinx_pwm_apply() when calculating the period_cycles and=0A= duty_cycles values. Since priv->max is a u32, this will=0A= result in an overflow to 1 which will not only be incorrect=0A= but fail on range comparison. This results in making it=0A= impossible to set the PWM in this timer mode.=0A= =0A= There are two obvious solutions to the current problem:=0A= 1. Cast each instance where overflow occurs to u64.=0A= 2. Change priv->max from a u32 to a u64.=0A= =0A= Solution #1 requires more code modifications, and leaves=0A= opportunity to introduce similar overflows if other math=0A= statements are added in the future. These may also go=0A= undetected if running in non 32-bit timer modes.=0A= =0A= Solution #2 is the much smaller and cleaner approach and=0A= thus the chosen method in this patch.=0A= =0A= This was tested on a Zynq UltraScale+ with multiple=0A= instances of the PWM IP.=0A= =0A= Signed-off-by: Ken Sloat =0A= ---=0A= Changes in v2:=0A= -Update commit comments to explain specifically where this=0A= problem occurs as well as compare solutions.=0A= =0A= ---=0A= include/clocksource/timer-xilinx.h | 2 +-=0A= 1 file changed, 1 insertion(+), 1 deletion(-)=0A= =0A= diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer= -xilinx.h=0A= index c0f56fe6d22a..d116f18de899 100644=0A= --- a/include/clocksource/timer-xilinx.h=0A= +++ b/include/clocksource/timer-xilinx.h=0A= @@ -41,7 +41,7 @@ struct regmap;=0A= struct xilinx_timer_priv {=0A= struct regmap *map;=0A= struct clk *clk;=0A= - u32 max;=0A= + u64 max;=0A= };=0A= =0A= /**=0A= -- =0A= 2.17.1=0A=